dm: i2c: Add functions to read and write a register

[oweals/u-boot.git] / drivers / mmc / socfpga_dw_mmc.c

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 417ca4c2ae6bde1800e8e8008f652e9ef1b5161c..eb69aed9dfb48cfa462489eb3e7fe99664e2d234 100644 (file)
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <dwmmc.h>
+#include <errno.h>
 #include <asm/arch/dwmmc.h>
 #include <asm/arch/clock_manager.h>
 #include <asm/arch/system_manager.h>
@@ -16,8 +17,6 @@ static const struct socfpga_clock_manager *clock_manager_base =
 static const struct socfpga_system_manager *system_manager_base =
                (void *)SOCFPGA_SYSMGR_ADDRESS;
 
-static char *SOCFPGA_NAME = "SOCFPGA DWMMC";
-
 static void socfpga_dwmci_clksel(struct dwmci_host *host)
 {
        unsigned int drvsel;
@@ -45,20 +44,28 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
 
 int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
 {
-       struct dwmci_host *host = NULL;
-       host = calloc(sizeof(struct dwmci_host), 1);
+       struct dwmci_host *host;
+       unsigned long clk = cm_get_mmc_controller_clk_hz();
+
+       if (clk == 0) {
+               printf("%s: MMC clock is zero!", __func__);
+               return -EINVAL;
+       }
+
+       /* calloc for zero init */
+       host = calloc(1, sizeof(struct dwmci_host));
        if (!host) {
-               printf("dwmci_host calloc fail!\n");
-               return -1;
+               printf("%s: calloc() failed!\n", __func__);
+               return -ENOMEM;
        }
 
-       host->name = SOCFPGA_NAME;
+       host->name = "SOCFPGA DWMMC";
        host->ioaddr = (void *)regbase;
        host->buswidth = bus_width;
        host->clksel = socfpga_dwmci_clksel;
        host->dev_index = index;
        /* fixed clock divide by 4 which due to the SDMMC wrapper */
-       host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ;
+       host->bus_hz = clk;
        host->fifoth_val = MSIZE(0x2) |
                RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
                TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);