*/
#include <common.h>
+#include <bouncebuf.h>
#include <clk.h>
#include <fdtdec.h>
+#include <log.h>
+#include <malloc.h>
#include <mmc.h>
#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
#include <linux/compat.h>
+#include <linux/delay.h>
#include <linux/dma-direction.h>
#include <linux/io.h>
#include <linux/sizes.h>
#define RENESAS_SDHI_MAX_TAP 3
+#define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
+
+static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
+ { 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11,
+ 15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
+ { 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15,
+ 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
+};
+
+static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9,
+ 15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
+};
+
+static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
+ { 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10,
+ 11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
+ { 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
+};
+
+static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
+ { 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15,
+ 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
+ { 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15,
+ 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
+};
+
+static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11,
+ 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
+};
+
+static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
+{
+ /* On R-Car Gen3, MMC0 is at 0xee140000 */
+ return (uintptr_t)(priv->regbase) == 0xee140000;
+}
+
static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
{
/* read mode */
struct tmio_sd_priv *priv = dev_get_priv(dev);
struct mmc *mmc = mmc_get_mmc_dev(dev);
unsigned long new_tap = priv->tap_set;
+ unsigned long error_tap = priv->tap_set;
u32 reg, smpcmp;
if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
new_tap = (priv->tap_set +
priv->tap_num + 1) % priv->tap_num;
+ error_tap = (priv->tap_set +
+ priv->tap_num - 1) % priv->tap_num;
break;
case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
new_tap = (priv->tap_set +
priv->tap_num - 1) % priv->tap_num;
+ error_tap = (priv->tap_set +
+ priv->tap_num + 1) % priv->tap_num;
break;
default:
return true; /* Need re-tune */
}
+ if (priv->hs400_bad_tap & BIT(new_tap)) {
+ /*
+ * New tap is bad tap (cannot change).
+ * Compare with HS200 tuning result.
+ * In HS200 tuning, when smpcmp[error_tap]
+ * is OK, retune is executed.
+ */
+ if (priv->smpcmp & BIT(error_tap))
+ return true; /* Need retune */
+
+ return false; /* cannot change */
+ }
+
priv->tap_set = new_tap;
} else {
if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
if (!priv->needs_adjust_hs400)
return;
+ if (!priv->adjust_hs400_calib_table)
+ return;
+
/*
* Enabled Manual adjust HS400 mode
*
* 1) Disabled Write Protect
* W(addr=0x00, WP_DISABLE_CODE)
- * 2) Read Calibration code and adjust
- * R(addr=0x26) - adjust value
- * 3) Enabled Manual Calibration
+ *
+ * 2) Read Calibration code
+ * read_value = R(addr=0x26)
+ * 3) Refer to calibration table
+ * Calibration code = table[read_value]
+ * 4) Enabled Manual Calibration
* W(addr=0x22, manual mode | Calibration code)
- * 4) Set Offset value to TMPPORT3 Reg
+ * 5) Set Offset value to TMPPORT3 Reg
*/
sd_scc_tmpport_write32(priv, 0x00,
RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
calib_code = sd_scc_tmpport_read32(priv, 0x26);
calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
- if (calib_code > priv->adjust_hs400_calibrate)
- calib_code -= priv->adjust_hs400_calibrate;
- else
- calib_code = 0;
sd_scc_tmpport_write32(priv, 0x22,
RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
- calib_code);
+ priv->adjust_hs400_calib_table[calib_code]);
tmio_sd_writel(priv, priv->adjust_hs400_offset,
RENESAS_SDHI_SCC_TMPPORT3);
struct mmc *mmc = mmc_get_mmc_dev(dev);
bool hs400 = (mmc->selected_mode == MMC_HS_400);
int ret, taps = hs400 ? priv->nrtaps : 8;
+ unsigned long new_tap;
u32 reg;
if (taps == 4) /* HS400 on 4tap SoC needs different clock */
RENESAS_SDHI_SCC_DTCNTL_TAPEN,
RENESAS_SDHI_SCC_DTCNTL);
+ /* Avoid bad TAP */
+ if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
+ new_tap = (priv->tap_set +
+ priv->tap_num + 1) % priv->tap_num;
+
+ if (priv->hs400_bad_tap & BIT(new_tap))
+ new_tap = (priv->tap_set +
+ priv->tap_num - 1) % priv->tap_num;
+
+ if (priv->hs400_bad_tap & BIT(new_tap)) {
+ new_tap = priv->tap_set;
+ debug("Three consecutive bad tap is prohibited\n");
+ }
+
+ priv->tap_set = new_tap;
+ tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
+ }
+
if (taps == 4) {
tmio_sd_writel(priv, priv->tap_set >> 1,
RENESAS_SDHI_SCC_TAPSET);
}
#endif
+#define RENESAS_SDHI_DMA_ALIGNMENT 128
+
+static int renesas_sdhi_addr_aligned_gen(uintptr_t ubuf,
+ size_t len, size_t len_aligned)
+{
+ /* Check if start is aligned */
+ if (!IS_ALIGNED(ubuf, RENESAS_SDHI_DMA_ALIGNMENT)) {
+ debug("Unaligned buffer address %lx\n", ubuf);
+ return 0;
+ }
+
+ /* Check if length is aligned */
+ if (len != len_aligned) {
+ debug("Unaligned buffer length %zu\n", len);
+ return 0;
+ }
+
+#ifdef CONFIG_PHYS_64BIT
+ /* Check if below 32bit boundary */
+ if ((ubuf >> 32) || (ubuf + len_aligned) >> 32) {
+ debug("Buffer above 32bit boundary %lx-%lx\n",
+ ubuf, ubuf + len_aligned);
+ return 0;
+ }
+#endif
+
+ /* Aligned */
+ return 1;
+}
+
+static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
+{
+ uintptr_t ubuf = (uintptr_t)state->user_buffer;
+
+ return renesas_sdhi_addr_aligned_gen(ubuf, state->len,
+ state->len_aligned);
+}
+
static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
struct mmc_data *data)
{
+ struct bounce_buffer bbstate;
+ unsigned int bbflags;
+ bool bbok = false;
+ size_t len;
+ void *buf;
int ret;
+ if (data) {
+ if (data->flags & MMC_DATA_READ) {
+ buf = data->dest;
+ bbflags = GEN_BB_WRITE;
+ } else {
+ buf = (void *)data->src;
+ bbflags = GEN_BB_READ;
+ }
+ len = data->blocks * data->blocksize;
+
+ ret = bounce_buffer_start_extalign(&bbstate, buf, len, bbflags,
+ RENESAS_SDHI_DMA_ALIGNMENT,
+ renesas_sdhi_addr_aligned);
+ /*
+ * If the amount of data to transfer is too large, we can get
+ * -ENOMEM when starting the bounce buffer. If that happens,
+ * fall back to PIO as it was before, otherwise use the BB.
+ */
+ if (!ret) {
+ bbok = true;
+ if (data->flags & MMC_DATA_READ)
+ data->dest = bbstate.bounce_buffer;
+ else
+ data->src = bbstate.bounce_buffer;
+ }
+ }
+
ret = tmio_sd_send_cmd(dev, cmd, data);
+
+ if (data && bbok) {
+ buf = bbstate.user_buffer;
+
+ bounce_buffer_stop(&bbstate);
+
+ if (data->flags & MMC_DATA_READ)
+ data->dest = buf;
+ else
+ data->src = buf;
+ }
+
if (ret)
return ret;
return 0;
}
+int renesas_sdhi_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct mmc *mmc = upriv->mmc;
+ size_t len = blkcnt * mmc->read_bl_len;
+ size_t len_align = roundup(len, RENESAS_SDHI_DMA_ALIGNMENT);
+
+ if (renesas_sdhi_addr_aligned_gen((uintptr_t)dst, len, len_align)) {
+ if (priv->quirks & TMIO_SD_CAP_16BIT)
+ return U16_MAX;
+ else
+ return U32_MAX;
+ } else {
+ return (CONFIG_SYS_MALLOC_LEN / 4) / mmc->read_bl_len;
+ }
+}
+
static const struct dm_mmc_ops renesas_sdhi_ops = {
.send_cmd = renesas_sdhi_send_cmd,
.set_ios = renesas_sdhi_set_ios,
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
.wait_dat0 = renesas_sdhi_wait_dat0,
#endif
+ .get_b_max = renesas_sdhi_get_b_max,
};
#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
static void renesas_sdhi_filter_caps(struct udevice *dev)
{
- struct tmio_sd_plat *plat = dev_get_platdata(dev);
struct tmio_sd_priv *priv = dev_get_priv(dev);
if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
return;
- /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1,ES1.2 */
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+ struct tmio_sd_plat *plat = dev_get_platdata(dev);
+
+ /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() <= 1)) ||
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
- (rmobile_get_cpu_rev_fraction() <= 2)))
+ (rmobile_get_cpu_rev_fraction() < 2)))
plat->cfg.host_caps &= ~MMC_MODE_HS400;
- /* M3W ES1.x for x>2 can use HS400 with manual adjustment */
+ /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
+ if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
+ (rmobile_get_cpu_rev_integer() >= 2)) ||
+ ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
+ (rmobile_get_cpu_rev_integer() == 1) &&
+ (rmobile_get_cpu_rev_fraction() == 2)) ||
+ (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
+ priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
+
+ /* H3 ES3.0 can use HS400 with manual adjustment */
+ if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
+ (rmobile_get_cpu_rev_integer() >= 3)) {
+ priv->adjust_hs400_enable = true;
+ priv->adjust_hs400_offset = 0;
+ priv->adjust_hs400_calib_table =
+ r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
+ }
+
+ /* M3W ES1.2 can use HS400 with manual adjustment */
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
(rmobile_get_cpu_rev_integer() == 1) &&
- (rmobile_get_cpu_rev_fraction() > 2)) {
+ (rmobile_get_cpu_rev_fraction() == 2)) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 3;
- priv->adjust_hs400_calibrate = 0x9;
+ priv->adjust_hs400_calib_table =
+ r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
+ }
+
+ /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
+ if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
+ (rmobile_get_cpu_rev_integer() == 1) &&
+ (rmobile_get_cpu_rev_fraction() > 2)) {
+ priv->adjust_hs400_enable = true;
+ priv->adjust_hs400_offset = 0;
+ priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
+ priv->adjust_hs400_calib_table =
+ r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
}
/* M3N can use HS400 with manual adjustment */
if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 3;
- priv->adjust_hs400_calibrate = 0x0;
+ priv->adjust_hs400_calib_table =
+ r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
}
/* E3 can use HS400 with manual adjustment */
if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
priv->adjust_hs400_enable = true;
priv->adjust_hs400_offset = 3;
- priv->adjust_hs400_calibrate = 0x4;
+ priv->adjust_hs400_calib_table =
+ r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
}
/* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
priv->nrtaps = 4;
else
priv->nrtaps = 8;
-
+#endif
/* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
(rmobile_get_cpu_rev_integer() <= 1)) ||
return ret;
}
+ priv->quirks = quirks;
ret = tmio_sd_probe(dev, quirks);
renesas_sdhi_filter_caps(dev);
projects / oweals / u-boot.git / blobdiff