struct msdc_compatible *dev_comp;
struct clk src_clk; /* for SD/MMC bus clock */
+ struct clk src_clk_cg; /* optional, MSDC source clock control gate */
struct clk h_clk; /* MSDC core clock */
u32 src_clk_freq; /* source clock */
bool builtin_cd;
/* card detection / write protection GPIOs */
-#ifdef CONFIG_DM_GPIO
+#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc gpio_wp;
struct gpio_desc gpio_cd;
#endif
break;
}
+ chksz = min(size, (u32)MSDC_FIFO_SIZE);
+
+ if (msdc_fifo_rx_bytes(host) >= chksz) {
+ msdc_fifo_read(host, ptr, chksz);
+ ptr += chksz;
+ size -= chksz;
+ }
+
if (status & MSDC_INT_XFER_COMPL) {
if (size) {
pr_err("data not fully read\n");
break;
}
-
- chksz = min(size, (u32)MSDC_FIFO_SIZE);
-
- if (msdc_fifo_rx_bytes(host) >= chksz) {
- msdc_fifo_read(host, ptr, chksz);
- ptr += chksz;
- size -= chksz;
- }
- }
+}
return ret;
}
return !(val & MSDC_PS_CDSTS);
}
-#ifdef CONFIG_DM_GPIO
+#if CONFIG_IS_ENABLED(DM_GPIO)
if (!host->gpio_cd.dev)
return 1;
static int msdc_ops_get_wp(struct udevice *dev)
{
+#if CONFIG_IS_ENABLED(DM_GPIO)
struct msdc_host *host = dev_get_priv(dev);
-#ifdef CONFIG_DM_GPIO
if (!host->gpio_wp.dev)
return 0;
{
clk_enable(&host->src_clk);
clk_enable(&host->h_clk);
+ if (host->src_clk_cg.dev)
+ clk_enable(&host->src_clk_cg);
}
static int msdc_drv_probe(struct udevice *dev)
if (ret < 0)
return ret;
-#ifdef CONFIG_DM_GPIO
+ clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
#endif
.enhance_rx = false
};
+static const struct msdc_compatible mt8516_compat = {
+ .clk_div_bits = 12,
+ .pad_tune0 = true,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+};
+
static const struct udevice_id msdc_ids[] = {
{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
+ { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
{}
};