mmc: fsl_esdhc: set Abort command type for CMD12

[oweals/u-boot.git] / drivers / mmc / fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 5c20627c1c18da0c99a8dbc1db2bf856223732d2..ea5f4bf6c0e2fdad333019576a9732e6690f515a 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -105,12 +105,9 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
        else if (cmd->resp_type & MMC_RSP_PRESENT)
                xfertyp |= XFERTYP_RSPTYP_48;
 
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
-       defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \
-       defined(CONFIG_PPC_T4160)
        if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
                xfertyp |= XFERTYP_CMDTYP_ABORT;
-#endif
+
        return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
 
@@ -252,8 +249,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
         * Rounding up to next power of 2
         * => timeout + 13 = log2(mmc->clock/4) + 1
         * => timeout + 13 = fls(mmc->clock/4)
+        *
+        * However, the MMC spec "It is strongly recommended for hosts to
+        * implement more than 500ms timeout value even if the card
+        * indicates the 250ms maximum busy length."  Even the previous
+        * value of 300ms is known to be insufficient for some cards.
+        * So, we use
+        * => timeout + 13 = fls(mmc->clock/2)
         */
-       timeout = fls(mmc->clock/4);
+       timeout = fls(mmc->clock/2);
        timeout -= 13;
 
        if (timeout > 14)
@@ -502,15 +506,22 @@ static void set_sysctl(struct mmc *mmc, uint clock)
 
        clk = (pre_div << 8) | (div << 4);
 
+#ifdef CONFIG_FSL_USDHC
+       esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+#else
        esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
+#endif
 
        esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 
        udelay(10000);
 
-       clk = SYSCTL_PEREN | SYSCTL_CKEN;
+#ifdef CONFIG_FSL_USDHC
+       esdhc_clrbits32(&regs->sysctl, SYSCTL_RSTA);
+#else
+       esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
 
-       esdhc_setbits32(&regs->sysctl, clk);
 }
 
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
@@ -585,7 +596,9 @@ static int esdhc_init(struct mmc *mmc)
        esdhc_write32(&regs->scr, 0x00000040);
 #endif
 
+#ifndef CONFIG_FSL_USDHC
        esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+#endif
 
        /* Set the initial clock speed */
        mmc_set_clock(mmc, 400000);
@@ -657,8 +670,10 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
        /* First reset the eSDHC controller */
        esdhc_reset(regs);
 
+#ifndef CONFIG_FSL_USDHC
        esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
                                | SYSCTL_IPGEN | SYSCTL_CKEN);
+#endif
 
        writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
        memset(&cfg->cfg, 0, sizeof(cfg->cfg));
@@ -753,6 +768,9 @@ void mmc_adapter_card_type_ident(void)
                QIXIS_WRITE(brdcfg[5], value);
                break;
        case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
+               value = QIXIS_READ(pwr_ctl[1]);
+               value |= QIXIS_EVDD_BY_SDHC_VS;
+               QIXIS_WRITE(pwr_ctl[1], value);
                break;
        case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
                value = QIXIS_READ(brdcfg[5]);