Merge git://git.denx.de/u-boot-mmc

[oweals/u-boot.git] / drivers / mmc / fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index b49a269e4bf23a2faebd63544afa0e11ae299523..71c62f42337b01073ca100b43a5e8fd4631b1249 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -171,20 +171,20 @@ static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
        uint databuf;
        uint size;
        uint irqstat;
-       uint timeout;
+       ulong start;
 
        if (data->flags & MMC_DATA_READ) {
                blocks = data->blocks;
                buffer = data->dest;
                while (blocks) {
-                       timeout = PIO_TIMEOUT;
+                       start = get_timer(0);
                        size = data->blocksize;
                        irqstat = esdhc_read32(&regs->irqstat);
-                       while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
-                               && --timeout);
-                       if (timeout <= 0) {
-                               printf("\nData Read Failed in PIO Mode.");
-                               return;
+                       while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
+                               if (get_timer(start) > PIO_TIMEOUT) {
+                                       printf("\nData Read Failed in PIO Mode.");
+                                       return;
+                               }
                        }
                        while (size && (!(irqstat & IRQSTAT_TC))) {
                                udelay(100); /* Wait before last byte transfer complete */
@@ -200,14 +200,14 @@ static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
                blocks = data->blocks;
                buffer = (char *)data->src;
                while (blocks) {
-                       timeout = PIO_TIMEOUT;
+                       start = get_timer(0);
                        size = data->blocksize;
                        irqstat = esdhc_read32(&regs->irqstat);
-                       while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
-                               && --timeout);
-                       if (timeout <= 0) {
-                               printf("\nData Write Failed in PIO Mode.");
-                               return;
+                       while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
+                               if (get_timer(start) > PIO_TIMEOUT) {
+                                       printf("\nData Write Failed in PIO Mode.");
+                                       return;
+                               }
                        }
                        while (size && (!(irqstat & IRQSTAT_TC))) {
                                udelay(100); /* Wait before last byte transfer complete */
@@ -647,7 +647,11 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
        esdhc_write32(&regs->clktunectrlstatus, 0x0);
 
        /* Put VEND_SPEC to default value */
-       esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
+       if (priv->vs18_enable)
+               esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
+                             ESDHC_VENDORSPEC_VSELECT));
+       else
+               esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
 
        /* Disable DLL_CTRL delay line */
        esdhc_write32(&regs->dllctrl, 0x0);
@@ -665,7 +669,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 #endif
 
        /* Set the initial clock speed */
-       mmc_set_clock(mmc, 400000);
+       mmc_set_clock(mmc, 400000, false);
 
        /* Disable the BRR and BWR bits in IRQSTAT */
        esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
@@ -676,9 +680,6 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
        /* Set timout to the maximum value */
        esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 
-       if (priv->vs18_enable)
-               esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-
        return 0;
 }
 
@@ -726,7 +727,7 @@ static int esdhc_reset(struct fsl_esdhc *regs)
        return 0;
 }
 
-#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
+#if !CONFIG_IS_ENABLED(DM_MMC)
 static int esdhc_getcd(struct mmc *mmc)
 {
        struct fsl_esdhc_priv *priv = mmc->priv;
@@ -820,7 +821,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
                voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
 
        cfg->name = "FSL_SDHC";
-#if !CONFIG_IS_ENABLED(DM_MMC_OPS)
+#if !CONFIG_IS_ENABLED(DM_MMC)
        cfg->ops = &esdhc_ops;
 #endif
 #ifdef CONFIG_SYS_SD_VOLTAGE
@@ -1127,7 +1128,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
        return esdhc_init_common(priv, mmc);
 }
 
-#if CONFIG_IS_ENABLED(DM_MMC_OPS)
+#if CONFIG_IS_ENABLED(DM_MMC)
 static int fsl_esdhc_get_cd(struct udevice *dev)
 {
        struct fsl_esdhc_priv *priv = dev_get_priv(dev);
@@ -1184,9 +1185,7 @@ U_BOOT_DRIVER(fsl_esdhc) = {
        .name   = "fsl-esdhc-mmc",
        .id     = UCLASS_MMC,
        .of_match = fsl_esdhc_ids,
-#if CONFIG_IS_ENABLED(DM_MMC_OPS)
        .ops    = &fsl_esdhc_ops,
-#endif
 #if CONFIG_IS_ENABLED(BLK)
        .bind   = fsl_esdhc_bind,
 #endif