Merge git://git.denx.de/u-boot-mpc85xx

[oweals/u-boot.git] / drivers / mmc / fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 471d6ee4a63bc63dcc06a9515542a2e054aad90b..1ccc576c347c6f0f669ab35e247641df252ba1eb 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -106,7 +106,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
                xfertyp |= XFERTYP_RSPTYP_48;
 
 #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
-       defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE)
+       defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE) || \
+       defined(CONFIG_PPC_T4160)
        if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
                xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
@@ -501,15 +502,22 @@ static void set_sysctl(struct mmc *mmc, uint clock)
 
        clk = (pre_div << 8) | (div << 4);
 
+#ifdef CONFIG_FSL_USDHC
+       esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+#else
        esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
+#endif
 
        esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 
        udelay(10000);
 
-       clk = SYSCTL_PEREN | SYSCTL_CKEN;
+#ifdef CONFIG_FSL_USDHC
+       esdhc_clrbits32(&regs->sysctl, SYSCTL_RSTA);
+#else
+       esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
 
-       esdhc_setbits32(&regs->sysctl, clk);
 }
 
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
@@ -584,7 +592,9 @@ static int esdhc_init(struct mmc *mmc)
        esdhc_write32(&regs->scr, 0x00000040);
 #endif
 
+#ifndef CONFIG_FSL_USDHC
        esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+#endif
 
        /* Set the initial clock speed */
        mmc_set_clock(mmc, 400000);
@@ -656,8 +666,10 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
        /* First reset the eSDHC controller */
        esdhc_reset(regs);
 
+#ifndef CONFIG_FSL_USDHC
        esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
                                | SYSCTL_IPGEN | SYSCTL_CKEN);
+#endif
 
        writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
        memset(&cfg->cfg, 0, sizeof(cfg->cfg));
@@ -747,8 +759,14 @@ void mmc_adapter_card_type_ident(void)
 
        switch (card_id) {
        case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
+               value = QIXIS_READ(brdcfg[5]);
+               value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
+               QIXIS_WRITE(brdcfg[5], value);
                break;
        case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
+               value = QIXIS_READ(pwr_ctl[1]);
+               value |= QIXIS_EVDD_BY_SDHC_VS;
+               QIXIS_WRITE(pwr_ctl[1], value);
                break;
        case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
                value = QIXIS_READ(brdcfg[5]);