mmc: add setdsr support

[oweals/u-boot.git] / drivers / mmc / exynos_dw_mmc.c

diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 4238dd933b016421e9b9afce8fa18e54f2b8871a..b3e5c5e5e09b5db5d04bfac1b8bd3093b9d3d655 100644 (file)
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -2,20 +2,7 @@
  * (C) Copyright 2012 SAMSUNG Electronics
  * Jaehoon Chung <jh80.chung@samsung.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,  MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -47,6 +34,19 @@ unsigned int exynos_dwmci_get_clk(int dev_index)
        return get_mmc_clk(dev_index);
 }
 
+static void exynos_dwmci_board_init(struct dwmci_host *host)
+{
+       if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+               dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
+               dwmci_writel(host, EMMCP_SEND0, 0);
+               dwmci_writel(host, EMMCP_CTRL0,
+                            MPSCTRL_SECURE_READ_BIT |
+                            MPSCTRL_SECURE_WRITE_BIT |
+                            MPSCTRL_NON_SECURE_READ_BIT |
+                            MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
+       }
+}
+
 /*
  * This function adds the mmc channel to be registered with mmc core.
  * index -     mmc channel number.
@@ -75,6 +75,10 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
        host->name = "EXYNOS DWMMC";
        host->ioaddr = (void *)regbase;
        host->buswidth = bus_width;
+#ifdef CONFIG_EXYNOS5420
+       host->quirks = DWMCI_QUIRK_DISABLE_SMU;
+#endif
+       host->board_init = exynos_dwmci_board_init;
 
        if (clksel) {
                host->clksel_val = clksel;
@@ -87,7 +91,7 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
 
        host->clksel = exynos_dwmci_clksel;
        host->dev_index = index;
-       host->mmc_clk = exynos_dwmci_get_clk;
+       host->get_mmc_clk = exynos_dwmci_get_clk;
        /* Add the mmc channel to be registered with mmc core */
        if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
                debug("dwmmc%d registration failed\n", index);