spl: Init proper struct driver member (platdata_auto_alloc_size) for mxs_spi

[oweals/u-boot.git] / drivers / mmc / Kconfig

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index b5180ea4a0682740b8d6db8c4b369c16ee5dc20c..7361bcaf8e4ec5a1f284361500f9fbae79d686c9 100644 (file)
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -46,6 +46,24 @@ config SPL_DM_MMC
 
 if MMC
 
+config MMC_SPI
+       bool "Support for SPI-based MMC controller"
+       depends on DM_MMC && DM_SPI
+       help
+         This selects SPI-based MMC controllers.
+         If you have an MMC controller on a SPI bus, say Y here.
+
+         If unsure, say N.
+
+config MMC_SPI_CRC_ON
+       bool "Support CRC for SPI-based MMC controller"
+       depends on MMC_SPI
+       default y
+       help
+         This enables CRC for SPI-based MMC controllers.
+
+         If unsure, say N.
+
 config ARM_PL180_MMCI
        bool "ARM AMBA Multimedia Card Interface and compatible support"
        depends on DM_MMC && OF_CONTROL
@@ -117,6 +135,18 @@ config SPL_MMC_UHS_SUPPORT
          cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus
          frequency can go up to 208MHz (SDR104)
 
+config MMC_HS400_ES_SUPPORT
+       bool "enable HS400 Enhanced Strobe support"
+       help
+         The HS400 Enhanced Strobe mode is support by some eMMC. The bus
+         frequency is up to 200MHz. This mode does not tune the IO.
+
+config SPL_MMC_HS400_ES_SUPPORT
+       bool "enable HS400 Enhanced Strobe support in SPL"
+       help
+         The HS400 Enhanced Strobe mode is support by some eMMC. The bus
+         frequency is up to 200MHz. This mode does not tune the IO.
+
 config MMC_HS400_SUPPORT
        bool "enable HS400 support"
        select MMC_HS200_SUPPORT
@@ -126,6 +156,7 @@ config MMC_HS400_SUPPORT
 
 config SPL_MMC_HS400_SUPPORT
        bool "enable HS400 support in SPL"
+       select SPL_MMC_HS200_SUPPORT
        help
          The HS400 mode is support by some eMMC. The bus frequency is up to
          200MHz. This mode requires tuning the IO.
@@ -136,7 +167,6 @@ config MMC_HS200_SUPPORT
          The HS200 mode is support by some eMMC. The bus frequency is up to
          200MHz. This mode requires tuning the IO.
 
-
 config SPL_MMC_HS200_SUPPORT
        bool "enable HS200 support in SPL"
        help
@@ -390,6 +420,17 @@ config SPL_MMC_SDHCI_ADMA
          This enables support for the ADMA (Advanced DMA) defined
          in the SD Host Controller Standard Specification Version 3.00 in SPL.
 
+config MMC_SDHCI_ASPEED
+       bool "Aspeed SDHCI controller"
+       depends on ARCH_ASPEED
+       depends on DM_MMC
+       depends on MMC_SDHCI
+       help
+         Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed
+         SoCs. This device is compatible with SD 3.0 and/or MMC 4.3
+         specifications. On the AST2600, the device is also compatible with
+         MMC 5.1 and eMMC 3.0.
+
 config MMC_SDHCI_ATMEL
        bool "Atmel SDHCI controller support"
        depends on ARCH_AT91
@@ -438,14 +479,15 @@ config MMC_SDHCI_CADENCE
 
          If unsure, say N.
 
-config MMC_SDHCI_K3_ARASAN
-       bool "Arasan SDHCI controller for TI's K3 based SoCs"
+config MMC_SDHCI_AM654
+       bool "SDHCI Controller on TI's Am654 devices"
        depends on ARCH_K3
        depends on MMC_SDHCI
        depends on DM_MMC && OF_CONTROL && BLK
+       depends on REGMAP
        help
-         Support for Arasan SDHCI host controller on Texas Instruments'
-         K3 family based SoC platforms
+         Support for Secure Digital Host Controller Interface (SDHCI)
+         controllers present on TI's AM654 SOCs.
 
 config MMC_SDHCI_KONA
        bool "SDHCI support on Broadcom KONA platform"
@@ -560,6 +602,17 @@ config MMC_SDHCI_TEGRA
 
          If unsure, say N.
 
+config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
+       bool "Disable external clock loopback"
+       depends on MMC_SDHCI_TEGRA && TEGRA124
+       help
+         Disable the external clock loopback and use the internal one on SDMMC3
+         as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
+         being set to 0xfffd according to the TRM.
+
+         TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
+         approach once proper kernel integration made it mainline.
+
 config MMC_SDHCI_ZYNQ
        bool "Arasan SDHCI controller support"
        depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
@@ -639,29 +692,34 @@ config MMC_MTK
 
 endif
 
-config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
-       bool "Disable external clock loopback"
-       depends on MMC_SDHCI_TEGRA && TEGRA124
-       help
-         Disable the external clock loopback and use the internal one on SDMMC3
-         as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
-         being set to 0xfffd according to the TRM.
-
-         TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
-         approach once proper kernel integration made it mainline.
-
 config FSL_ESDHC
        bool "Freescale/NXP eSDHC controller support"
+       select FSL_ESDHC_USE_PERIPHERAL_CLK if MMC_HS200_SUPPORT || MMC_UHS_SUPPORT
        help
          This selects support for the eSDHC (Enhanced Secure Digital Host
          Controller) found on numerous Freescale/NXP SoCs.
 
+config FSL_ESDHC_USE_PERIPHERAL_CLK
+       bool "enable ESDHC peripheral clock support"
+       depends on FSL_ESDHC
+       help
+         eSDHC supports two reference clocks (platform clock and peripheral clock).
+         Peripheral clock which could provide higher clock frequency is required to
+         be used for tuning of SD UHS mode and eMMC HS200/HS400 modes.
+
 config FSL_ESDHC_IMX
        bool "Freescale/NXP i.MX eSDHC controller support"
        help
          This selects support for the i.MX eSDHC (Enhanced Secure Digital Host
          Controller) found on numerous Freescale/NXP SoCs.
 
+config FSL_USDHC
+       bool "Freescale/NXP i.MX uSDHC controller support"
+       depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || TARGET_S32V234EVB
+       select FSL_ESDHC_IMX
+       help
+         This enables the Ultra Secured Digital Host Controller enhancements
+
 endmenu
 
 config SYS_FSL_ERRATUM_ESDHC111