set of generic read, write and ioctl methods may be used to
access the device.
+config SPL_MISC
+ bool "Enable Driver Model for Misc drivers in SPL"
+ depends on SPL_DM
+ help
+ Enable driver model for miscellaneous devices. This class is
+ used only for those do not fit other more general classes. A
+ set of generic read, write and ioctl methods may be used to
+ access the device.
+
+config TPL_MISC
+ bool "Enable Driver Model for Misc drivers in TPL"
+ depends on TPL_DM
+ help
+ Enable driver model for miscellaneous devices. This class is
+ used only for those do not fit other more general classes. A
+ set of generic read, write and ioctl methods may be used to
+ access the device.
+
config ALTERA_SYSID
bool "Altera Sysid support"
depends on MISC
extended (by porting the read function from the Linux kernel sources)
to support other recent Rockchip devices.
+config ROCKCHIP_OTP
+ bool "Rockchip OTP Support"
+ depends on MISC
+ help
+ Enable (read-only) access for the one-time-programmable memory block
+ found in Rockchip SoCs: accesses can either be made using byte
+ addressing and a length or through child-nodes that are generated
+ based on the e-fuse map retrieved from the DTS.
+
config VEXPRESS_CONFIG
bool "Enable support for Arm Versatile Express config bus"
depends on MISC
control access to the battery and main PMIC depending on the
device. You can use the 'crosec' command to access it.
+config SPL_CROS_EC
+ bool "Enable Chrome OS EC in SPL"
+ depends on SPL
+ help
+ Enable access to the Chrome OS EC in SPL. This is a separate
+ microcontroller typically available on a SPI bus on Chromebooks. It
+ provides access to the keyboard, some internal storage and may
+ control access to the battery and main PMIC depending on the
+ device. You can use the 'crosec' command to access it.
+
+config TPL_CROS_EC
+ bool "Enable Chrome OS EC in TPL"
+ depends on TPL
+ help
+ Enable access to the Chrome OS EC in TPL. This is a separate
+ microcontroller typically available on a SPI bus on Chromebooks. It
+ provides access to the keyboard, some internal storage and may
+ control access to the battery and main PMIC depending on the
+ device. You can use the 'crosec' command to access it.
+
config CROS_EC_I2C
bool "Enable Chrome OS EC I2C driver"
depends on CROS_EC
through a legacy port interface, so on x86 machines the main
function of the EC is power and thermal management.
+config SPL_CROS_EC_LPC
+ bool "Enable Chrome OS EC LPC driver in SPL"
+ depends on CROS_EC
+ help
+ Enable I2C access to the Chrome OS EC. This is used on x86
+ Chromebooks such as link and falco. The keyboard is provided
+ through a legacy port interface, so on x86 machines the main
+ function of the EC is power and thermal management.
+
+config TPL_CROS_EC_LPC
+ bool "Enable Chrome OS EC LPC driver in TPL"
+ depends on CROS_EC
+ help
+ Enable I2C access to the Chrome OS EC. This is used on x86
+ Chromebooks such as link and falco. The keyboard is provided
+ through a legacy port interface, so on x86 machines the main
+ function of the EC is power and thermal management.
+
config CROS_EC_SANDBOX
bool "Enable Chrome OS EC sandbox driver"
depends on CROS_EC && SANDBOX
EC flash read/write/erase support and a few other things. It is
enough to perform a Chrome OS verified boot on sandbox.
+config SPL_CROS_EC_SANDBOX
+ bool "Enable Chrome OS EC sandbox driver in SPL"
+ depends on SPL_CROS_EC && SANDBOX
+ help
+ Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
+ keyboard (use the -l flag to enable the LCD), verified boot context,
+ EC flash read/write/erase support and a few other things. It is
+ enough to perform a Chrome OS verified boot on sandbox.
+
+config TPL_CROS_EC_SANDBOX
+ bool "Enable Chrome OS EC sandbox driver in TPL"
+ depends on TPL_CROS_EC && SANDBOX
+ help
+ Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
+ keyboard (use the -l flag to enable the LCD), verified boot context,
+ EC flash read/write/erase support and a few other things. It is
+ enough to perform a Chrome OS verified boot on sandbox.
+
config CROS_EC_SPI
bool "Enable Chrome OS EC SPI driver"
depends on CROS_EC
Security Monitor can be transitioned on any security failures,
like software violations or hardware security violations.
+config IRQ
+ bool "Intel Interrupt controller"
+ depends on X86 || SANDBOX
+ help
+ This enables support for Intel interrupt controllers, including ITSS.
+ Some devices have extra features, such as Apollo Lake. The
+ device has its own uclass since there are several operations
+ involved.
+
config JZ4780_EFUSE
bool "Ingenic JZ4780 eFUSE support"
depends on ARCH_JZ47XX
config MXC_OCOTP
bool "Enable MXC OCOTP Driver"
+ depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
+ default y
help
If you say Y here, you will get support for the One Time
Programmable memory pages that are stored on the some
disable the legacy UART, the watchdog or other devices
in the Nuvoton Super IO chips on X86 platforms.
+config P2SB
+ bool "Intel Primary-to-Sideband Bus"
+ depends on X86 || SANDBOX
+ help
+ This enables support for the Intel Primary-to-Sideband bus,
+ abbreviated to P2SB. The P2SB is used to access various peripherals
+ such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
+ space. The space is segmented into different channels and peripherals
+ are accessed by device-specific means within those channels. Devices
+ should be added in the device tree as subnodes of the P2SB. A
+ Peripheral Channel Register? (PCR) API is provided to access those
+ devices - see pcr_readl(), etc.
+
+config SPL_P2SB
+ bool "Intel Primary-to-Sideband Bus in SPL"
+ depends on SPL && (X86 || SANDBOX)
+ help
+ The Primary-to-Sideband bus is used to access various peripherals
+ through memory-mapped I/O in a large chunk of PCI space. The space is
+ segmented into different channels and peripherals are accessed by
+ device-specific means within those channels. Devices should be added
+ in the device tree as subnodes of the p2sb.
+
+config TPL_P2SB
+ bool "Intel Primary-to-Sideband Bus in TPL"
+ depends on TPL && (X86 || SANDBOX)
+ help
+ The Primary-to-Sideband bus is used to access various peripherals
+ through memory-mapped I/O in a large chunk of PCI space. The space is
+ segmented into different channels and peripherals are accessed by
+ device-specific means within those channels. Devices should be added
+ in the device tree as subnodes of the p2sb.
+
config PWRSEQ
bool "Enable power-sequencing drivers"
depends on DM
config STM32_RCC
bool "Enable RCC driver for the STM32 SoC's family"
- depends on (STM32 || ARCH_STM32MP) && MISC
+ depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
help
Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
block) is responsible of the management of the clock and reset
gdsys devices, which supply the majority of the functionality offered
by the devices. This driver supports both CON and CPU variants of the
devices, depending on the device tree entry.
+config ESM_K3
+ bool "Enable K3 ESM driver"
+ depends on ARCH_K3
+ help
+ Support ESM (Error Signaling Module) on TI K3 SoCs.
+
+config MICROCHIP_FLEXCOM
+ bool "Enable Microchip Flexcom driver"
+ depends on MISC
+ help
+ The Atmel Flexcom is just a wrapper which embeds a SPI controller,
+ an I2C controller and an USART.
+ Only one function can be used at a time and is chosen at boot time
+ according to the device tree.
+
+config K3_AVS0
+ depends on ARCH_K3 && SPL_DM_REGULATOR
+ bool "AVS class 0 support for K3 devices"
+ help
+ K3 devices have the optimized voltage values for the main voltage
+ domains stored in efuse within the VTM IP. This driver reads the
+ optimized voltage from the efuse, so that it can be programmed
+ to the PMIC on board.
+
+config ESM_PMIC
+ bool "Enable PMIC ESM driver"
+ depends on DM_PMIC
+ help
+ Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
+ typically to reboot the board in error condition.
endmenu
projects / oweals / u-boot.git / blobdiff