mtd: spi: Add a new option SPL_SPI_FLASH_MTD to Kconfig

[oweals/u-boot.git] / drivers / mailbox / tegra-hsp.c

diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c
index 5c781a50b6aca9a7b222a6d8f23e438dd0975cae..9bee886561c5296cdd8a226ef7d6e1478db0c9bd 100644 (file)
--- a/drivers/mailbox/tegra-hsp.c
+++ b/drivers/mailbox/tegra-hsp.c
@@ -1,14 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2016, NVIDIA CORPORATION.
- *
- * SPDX-License-Identifier: GPL-2.0
  */
 
 #include <common.h>
 #include <asm/io.h>
 #include <dm.h>
 #include <mailbox-uclass.h>
-#include <dt-bindings/mailbox/tegra-hsp.h>
+#include <dt-bindings/mailbox/tegra186-hsp.h>
+
+#define TEGRA_HSP_INT_DIMENSIONING             0x380
+#define TEGRA_HSP_INT_DIMENSIONING_NSI_SHIFT   16
+#define TEGRA_HSP_INT_DIMENSIONING_NSI_MASK    0xf
+#define TEGRA_HSP_INT_DIMENSIONING_NDB_SHIFT   12
+#define TEGRA_HSP_INT_DIMENSIONING_NDB_MASK    0xf
+#define TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT   8
+#define TEGRA_HSP_INT_DIMENSIONING_NAS_MASK    0xf
+#define TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT   4
+#define TEGRA_HSP_INT_DIMENSIONING_NSS_MASK    0xf
+#define TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT   0
+#define TEGRA_HSP_INT_DIMENSIONING_NSM_MASK    0xf
 
 #define TEGRA_HSP_DB_REG_TRIGGER       0x0
 #define TEGRA_HSP_DB_REG_ENABLE                0x4
@@ -24,8 +35,6 @@ struct tegra_hsp {
        uint32_t db_base;
 };
 
-DECLARE_GLOBAL_DATA_PTR;
-
 static uint32_t *tegra_hsp_reg(struct tegra_hsp *thsp, uint32_t db_id,
                               uint32_t reg)
 {
@@ -51,7 +60,7 @@ static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val,
 static int tegra_hsp_db_id(ulong chan_id)
 {
        switch (chan_id) {
-       case TEGRA_HSP_MASTER_BPMP:
+       case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP:
                return TEGRA_HSP_DB_ID_BPMP;
        default:
                debug("Invalid channel ID\n");
@@ -59,6 +68,21 @@ static int tegra_hsp_db_id(ulong chan_id)
        }
 }
 
+static int tegra_hsp_of_xlate(struct mbox_chan *chan,
+                             struct ofnode_phandle_args *args)
+{
+       debug("%s(chan=%p)\n", __func__, chan);
+
+       if (args->args_count != 2) {
+               debug("Invaild args_count: %d\n", args->args_count);
+               return -EINVAL;
+       }
+
+       chan->id = (args->args[0] << 16) | args->args[1];
+
+       return 0;
+}
+
 static int tegra_hsp_request(struct mbox_chan *chan)
 {
        int db_id;
@@ -121,20 +145,23 @@ static int tegra_hsp_bind(struct udevice *dev)
 static int tegra_hsp_probe(struct udevice *dev)
 {
        struct tegra_hsp *thsp = dev_get_priv(dev);
+       u32 val;
        int nr_sm, nr_ss, nr_as;
 
        debug("%s(dev=%p)\n", __func__, dev);
 
-       thsp->regs = dev_get_addr(dev);
+       thsp->regs = devfdt_get_addr(dev);
        if (thsp->regs == FDT_ADDR_T_NONE)
                return -ENODEV;
 
-       nr_sm = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SM",
-                              0);
-       nr_ss = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SS",
-                              0);
-       nr_as = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-AS",
-                              0);
+       val = readl(thsp->regs + TEGRA_HSP_INT_DIMENSIONING);
+       nr_sm = (val >> TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT) &
+               TEGRA_HSP_INT_DIMENSIONING_NSM_MASK;
+       nr_ss = (val >> TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT) &
+               TEGRA_HSP_INT_DIMENSIONING_NSS_MASK;
+       nr_as = (val >> TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT) &
+               TEGRA_HSP_INT_DIMENSIONING_NAS_MASK;
+
        thsp->db_base = (1 + (nr_sm >> 1) + nr_ss + nr_as) << 16;
 
        return 0;
@@ -146,6 +173,7 @@ static const struct udevice_id tegra_hsp_ids[] = {
 };
 
 struct mbox_ops tegra_hsp_mbox_ops = {
+       .of_xlate = tegra_hsp_of_xlate,
        .request = tegra_hsp_request,
        .free = tegra_hsp_free,
        .send = tegra_hsp_send,