/*
- * i2c driver for Freescale mx31
+ * i2c driver for Freescale i.MX series
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on i2c-imx.c from linux kernel:
+ * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
+ * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
+ * Copyright (C) 2007 RightHand Technologies, Inc.
+ * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
+ *
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#include <common.h>
+#include <asm/io.h>
#if defined(CONFIG_HARD_I2C)
-#include <asm/arch/mx31.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <i2c.h>
-#define IADR 0x00
-#define IFDR 0x04
-#define I2CR 0x08
-#define I2SR 0x0c
-#define I2DR 0x10
+struct mxc_i2c_regs {
+ uint32_t iadr;
+ uint32_t ifdr;
+ uint32_t i2cr;
+ uint32_t i2sr;
+ uint32_t i2dr;
+};
#define I2CR_IEN (1 << 7)
#define I2CR_IIEN (1 << 6)
#define I2SR_IIF (1 << 1)
#define I2SR_RX_NO_AK (1 << 0)
-#ifdef CFG_I2C_MX31_PORT1
-#define I2C_BASE 0x43f80000
-#elif defined (CFG_I2C_MX31_PORT2)
-#define I2C_BASE 0x43f98000
-#elif defined (CFG_I2C_MX31_PORT3)
-#define I2C_BASE 0x43f84000
+#ifdef CONFIG_SYS_I2C_BASE
+#define I2C_BASE CONFIG_SYS_I2C_BASE
#else
-#error "define CFG_I2C_MX31_PORTx to use the mx31 I2C driver"
+#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
#endif
-#ifdef DEBUG
-#define DPRINTF(args...) printf(args)
-#else
-#define DPRINTF(args...)
+#define I2C_MAX_TIMEOUT 10000
+
+static u16 i2c_clk_div[50][2] = {
+ { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
+ { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
+ { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
+ { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
+ { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
+ { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
+ { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
+ { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
+ { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
+ { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
+ { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
+ { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
+ { 3072, 0x1E }, { 3840, 0x1F }
+};
+
+/*
+ * Calculate and set proper clock divider
+ */
+static uint8_t i2c_imx_get_clk(unsigned int rate)
+{
+ unsigned int i2c_clk_rate;
+ unsigned int div;
+ u8 clk_div;
+
+#if defined(CONFIG_MX31)
+ struct clock_control_regs *sc_regs =
+ (struct clock_control_regs *)CCM_BASE;
+
+ /* start the required I2C clock */
+ writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
+ &sc_regs->cgr0);
#endif
-static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
- 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960,
- 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840};
+ /* Divider value calculation */
+ i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK);
+ div = (i2c_clk_rate + rate - 1) / rate;
+ if (div < i2c_clk_div[0][0])
+ clk_div = 0;
+ else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
+ clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
+ else
+ for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
+ ;
+
+ /* Store divider value */
+ return clk_div;
+}
+
+/*
+ * Reset I2C Controller
+ */
+void i2c_reset(void)
+{
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+
+ writeb(0, &i2c_regs->i2cr); /* Reset module */
+ writeb(0, &i2c_regs->i2sr);
+}
+/*
+ * Init I2C Bus
+ */
void i2c_init(int speed, int unused)
{
- int freq = mx31_get_ipg_clk();
- int i;
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+ u8 clk_idx = i2c_imx_get_clk(speed);
+ u8 idx = i2c_clk_div[clk_idx][1];
- for (i = 0; i < 0x1f; i++)
- if (freq / div[i] <= speed)
- break;
+ /* Store divider value */
+ writeb(idx, &i2c_regs->ifdr);
+
+ i2c_reset();
+}
+
+/*
+ * Set I2C Speed
+ */
+int i2c_set_bus_speed(unsigned int speed)
+{
+ i2c_init(speed, 0);
+ return 0;
+}
- DPRINTF("%s: speed: %d\n",__FUNCTION__, speed);
+/*
+ * Get I2C Speed
+ */
+unsigned int i2c_get_bus_speed(void)
+{
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+ u8 clk_idx = readb(&i2c_regs->ifdr);
+ u8 clk_div;
+
+ for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
+ ;
- __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
- __REG16(I2C_BASE + IFDR) = i;
- __REG16(I2C_BASE + I2CR) = I2CR_IEN;
- __REG16(I2C_BASE + I2SR) = 0;
+ return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
}
-static int wait_busy(void)
+/*
+ * Wait for bus to be busy (or free if for_busy = 0)
+ *
+ * for_busy = 1: Wait for IBB to be asserted
+ * for_busy = 0: Wait for IBB to be de-asserted
+ */
+int i2c_imx_bus_busy(int for_busy)
{
- int timeout = 10000;
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+ unsigned int temp;
+
+ int timeout = I2C_MAX_TIMEOUT;
+
+ while (timeout--) {
+ temp = readb(&i2c_regs->i2sr);
+
+ if (for_busy && (temp & I2SR_IBB))
+ return 0;
+ if (!for_busy && !(temp & I2SR_IBB))
+ return 0;
- while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout)
udelay(1);
- __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
+ }
- return timeout;
+ return 1;
}
-static int tx_byte(u8 byte)
+/*
+ * Wait for transaction to complete
+ */
+int i2c_imx_trx_complete(void)
{
- __REG16(I2C_BASE + I2DR) = byte;
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+ int timeout = I2C_MAX_TIMEOUT;
- if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK)
- return -1;
- return 0;
+ while (timeout--) {
+ if (readb(&i2c_regs->i2sr) & I2SR_IIF) {
+ writeb(0, &i2c_regs->i2sr);
+ return 0;
+ }
+
+ udelay(1);
+ }
+
+ return 1;
}
-static int rx_byte(void)
+/*
+ * Check if the transaction was ACKed
+ */
+int i2c_imx_acked(void)
{
- if (!wait_busy())
- return -1;
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
- return __REG16(I2C_BASE + I2DR);
+ return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK;
}
-int i2c_probe(uchar chip)
+/*
+ * Start the controller
+ */
+int i2c_imx_start(void)
{
- int ret;
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+ unsigned int temp = 0;
+ int result;
- __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
- __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+ /* Enable I2C controller */
+ writeb(0, &i2c_regs->i2sr);
+ writeb(I2CR_IEN, &i2c_regs->i2cr);
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
- ret = tx_byte(chip << 1);
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX;
+ /* Wait controller to be stable */
+ udelay(50);
- return ret;
+ /* Start I2C transaction */
+ temp = readb(&i2c_regs->i2cr);
+ temp |= I2CR_MSTA;
+ writeb(temp, &i2c_regs->i2cr);
+
+ result = i2c_imx_bus_busy(1);
+ if (result)
+ return result;
+
+ temp |= I2CR_MTX | I2CR_TX_NO_AK;
+ writeb(temp, &i2c_regs->i2cr);
+
+ return 0;
}
-static int i2c_addr(uchar chip, uint addr, int alen)
+/*
+ * Stop the controller
+ */
+void i2c_imx_stop(void)
{
- __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+ unsigned int temp = 0;
- if (tx_byte(chip << 1))
- return -1;
+ /* Stop I2C transaction */
+ temp = readb(&i2c_regs->i2cr);
+ temp |= ~(I2CR_MSTA | I2CR_MTX);
+ writeb(temp, &i2c_regs->i2cr);
- while (alen--)
- if (tx_byte((addr >> (alen * 8)) & 0xff))
- return -1;
- return 0;
+ i2c_imx_bus_busy(0);
+
+ /* Disable I2C controller */
+ writeb(0, &i2c_regs->i2cr);
}
-int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+/*
+ * Set chip address and access mode
+ *
+ * read = 1: READ access
+ * read = 0: WRITE access
+ */
+int i2c_imx_set_chip_addr(uchar chip, int read)
{
- int timeout = 10000;
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
int ret;
- DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len);
+ writeb((chip << 1) | read, &i2c_regs->i2dr);
- if (i2c_addr(chip, addr, alen)) {
- printf("i2c_addr failed\n");
- return -1;
- }
+ ret = i2c_imx_trx_complete();
+ if (ret)
+ return ret;
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA;
+ ret = i2c_imx_acked();
+ if (ret)
+ return ret;
- if (tx_byte(chip << 1 | 1))
- return -1;
+ return ret;
+}
+
+/*
+ * Write register address
+ */
+int i2c_imx_set_reg_addr(uint addr, int alen)
+{
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+ int ret = 0;
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) ? I2CR_TX_NO_AK : 0);
+ while (alen--) {
+ writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr);
- ret = __REG16(I2C_BASE + I2DR);
+ ret = i2c_imx_trx_complete();
+ if (ret)
+ break;
- while (len--) {
- if ((ret = rx_byte()) < 0)
- return -1;
- *buf++ = ret;
- if (len <= 1)
- __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_TX_NO_AK;
+ ret = i2c_imx_acked();
+ if (ret)
+ break;
}
- wait_busy();
+ return ret;
+}
+
+/*
+ * Try if a chip add given address responds (probe the chip)
+ */
+int i2c_probe(uchar chip)
+{
+ int ret;
- __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+ ret = i2c_imx_start();
+ if (ret)
+ return ret;
- while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
- udelay(1);
+ ret = i2c_imx_set_chip_addr(chip, 0);
+ if (ret)
+ return ret;
- return 0;
+ i2c_imx_stop();
+
+ return ret;
}
+/*
+ * Read data from I2C device
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
+{
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+ int ret;
+ unsigned int temp;
+ int i;
+
+ ret = i2c_imx_start();
+ if (ret)
+ return ret;
+
+ /* write slave address */
+ ret = i2c_imx_set_chip_addr(chip, 0);
+ if (ret)
+ return ret;
+
+ ret = i2c_imx_set_reg_addr(addr, alen);
+ if (ret)
+ return ret;
+
+ temp = readb(&i2c_regs->i2cr);
+ temp |= I2CR_RSTA;
+ writeb(temp, &i2c_regs->i2cr);
+
+ ret = i2c_imx_set_chip_addr(chip, 1);
+ if (ret)
+ return ret;
+
+ /* setup bus to read data */
+ temp = readb(&i2c_regs->i2cr);
+ temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
+ if (len == 1)
+ temp |= I2CR_TX_NO_AK;
+ writeb(temp, &i2c_regs->i2cr);
+ readb(&i2c_regs->i2dr);
+
+ /* read data */
+ for (i = 0; i < len; i++) {
+ ret = i2c_imx_trx_complete();
+ if (ret)
+ return ret;
+
+ /*
+ * It must generate STOP before read I2DR to prevent
+ * controller from generating another clock cycle
+ */
+ if (i == (len - 1)) {
+ temp = readb(&i2c_regs->i2cr);
+ temp &= ~(I2CR_MSTA | I2CR_MTX);
+ writeb(temp, &i2c_regs->i2cr);
+ i2c_imx_bus_busy(0);
+ } else if (i == (len - 2)) {
+ temp = readb(&i2c_regs->i2cr);
+ temp |= I2CR_TX_NO_AK;
+ writeb(temp, &i2c_regs->i2cr);
+ }
+
+ buf[i] = readb(&i2c_regs->i2dr);
+ }
+
+ i2c_imx_stop();
+
+ return ret;
+}
+
+/*
+ * Write data to I2C device
+ */
int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
{
- int timeout = 10000;
- DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len);
+ struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+ int ret;
+ int i;
- if (i2c_addr(chip, addr, alen))
- return -1;
+ ret = i2c_imx_start();
+ if (ret)
+ return ret;
- while (len--)
- if (tx_byte(*buf++))
- return -1;
+ /* write slave address */
+ ret = i2c_imx_set_chip_addr(chip, 0);
+ if (ret)
+ return ret;
- __REG16(I2C_BASE + I2CR) = I2CR_IEN;
+ ret = i2c_imx_set_reg_addr(addr, alen);
+ if (ret)
+ return ret;
- while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
- udelay(1);
+ for (i = 0; i < len; i++) {
+ writeb(buf[i], &i2c_regs->i2dr);
- return 0;
-}
+ ret = i2c_imx_trx_complete();
+ if (ret)
+ return ret;
+
+ ret = i2c_imx_acked();
+ if (ret)
+ return ret;
+ }
+ i2c_imx_stop();
+
+ return ret;
+}
#endif /* CONFIG_HARD_I2C */