+// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx Zynq GPIO device driver
*
*
* Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
* Copyright (C) 2009 - 2014 Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
#include <dm.h>
#include <fdtdec.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/* Maximum banks */
#define ZYNQ_GPIO_MAX_BANK 4
/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
-struct zynq_gpio_privdata {
+#define PMC_GPIO_NR_GPIOS 116
+#define PMC_GPIO_MAX_BANK 5
+
+struct zynq_gpio_platdata {
phys_addr_t base;
const struct zynq_platform_data *p_data;
};
struct zynq_platform_data {
const char *label;
u16 ngpio;
- int max_bank;
- int bank_min[ZYNQMP_GPIO_MAX_BANK];
- int bank_max[ZYNQMP_GPIO_MAX_BANK];
+ u32 max_bank;
+ u32 bank_min[ZYNQMP_GPIO_MAX_BANK];
+ u32 bank_max[ZYNQMP_GPIO_MAX_BANK];
+};
+
+#define VERSAL_GPIO_NR_GPIOS 58
+#define VERSAL_GPIO_MAX_BANK 4
+
+static const struct zynq_platform_data versal_gpio_def = {
+ .label = "versal_gpio",
+ .ngpio = VERSAL_GPIO_NR_GPIOS,
+ .max_bank = VERSAL_GPIO_MAX_BANK,
+ .bank_min[0] = 0,
+ .bank_max[0] = 25,
+ .bank_min[3] = 26,
+ .bank_max[3] = 57,
+};
+
+static const struct zynq_platform_data pmc_gpio_def = {
+ .label = "pmc_gpio",
+ .ngpio = PMC_GPIO_NR_GPIOS,
+ .max_bank = PMC_GPIO_MAX_BANK,
+ .bank_min[0] = 0,
+ .bank_max[0] = 25,
+ .bank_min[1] = 26,
+ .bank_max[1] = 51,
+ .bank_min[3] = 52,
+ .bank_max[3] = 83,
+ .bank_min[4] = 84,
+ .bank_max[4] = 115,
};
static const struct zynq_platform_data zynqmp_gpio_def = {
unsigned int *bank_pin_num,
struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
- int bank;
-
- for (bank = 0; bank < priv->p_data->max_bank; bank++) {
- if ((pin_num >= priv->p_data->bank_min[bank]) &&
- (pin_num <= priv->p_data->bank_max[bank])) {
- *bank_num = bank;
- *bank_pin_num = pin_num -
- priv->p_data->bank_min[bank];
- return;
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+ u32 bank;
+
+ for (bank = 0; bank < platdata->p_data->max_bank; bank++) {
+ if (pin_num >= platdata->p_data->bank_min[bank] &&
+ pin_num <= platdata->p_data->bank_max[bank]) {
+ *bank_num = bank;
+ *bank_pin_num = pin_num -
+ platdata->p_data->bank_min[bank];
+ return;
}
}
- if (bank >= priv->p_data->max_bank) {
- printf("Inavlid bank and pin num\n");
+ if (bank >= platdata->p_data->max_bank) {
+ printf("Invalid bank and pin num\n");
*bank_num = 0;
*bank_pin_num = 0;
}
static int gpio_is_valid(unsigned gpio, struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
- return (gpio >= 0) && (gpio < priv->p_data->ngpio);
+ return gpio < platdata->p_data->ngpio;
}
static int check_gpio(unsigned gpio, struct udevice *dev)
{
u32 data;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
- data = readl(priv->base +
+ data = readl(platdata->base +
ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
return (data >> bank_pin_num) & 1;
static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
{
unsigned int reg_offset, bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
- writel(value, priv->base + reg_offset);
+ writel(value, platdata->base + reg_offset);
return 0;
}
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
return -1;
/* clear the bit in direction mode reg to set the pin as input */
- reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= ~BIT(bank_pin_num);
- writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
return 0;
}
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(gpio, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
/* set the GPIO pin as output */
- reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
- writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
/* configure the output enable reg for the pin */
- reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
reg |= BIT(bank_pin_num);
- writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+ writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
/* set the state of the pin */
- gpio_set_value(gpio, value);
+ zynq_gpio_set_value(dev, gpio, value);
return 0;
}
{
u32 reg;
unsigned int bank_num, bank_pin_num;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
if (check_gpio(offset, dev) < 0)
return -1;
zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
/* set the GPIO pin as output */
- reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+ reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
reg &= BIT(bank_pin_num);
if (reg)
return GPIOF_OUTPUT;
.get_value = zynq_gpio_get_value,
.set_value = zynq_gpio_set_value,
.get_function = zynq_gpio_get_function,
-
};
static const struct udevice_id zynq_gpio_ids[] = {
.data = (ulong)&zynq_gpio_def},
{ .compatible = "xlnx,zynqmp-gpio-1.0",
.data = (ulong)&zynqmp_gpio_def},
+ { .compatible = "xlnx,versal-gpio-1.0",
+ .data = (ulong)&versal_gpio_def},
+ { .compatible = "xlnx,pmc-gpio-1.0",
+ .data = (ulong)&pmc_gpio_def },
{ }
};
-static void zynq_gpio_getplat_data(struct udevice *dev)
-{
- const struct udevice_id *of_match = zynq_gpio_ids;
- int ret;
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
-
- while (of_match->compatible) {
- ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- of_match->compatible);
- if (ret >= 0) {
- priv->p_data =
- (struct zynq_platform_data *)of_match->data;
- break;
- } else {
- of_match++;
- continue;
- }
- }
-
- if (!priv->p_data)
- printf("No Platform data found\n");
-}
-
static int zynq_gpio_probe(struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ const void *label_ptr;
- zynq_gpio_getplat_data(dev);
+ label_ptr = dev_read_prop(dev, "label", NULL);
+ if (label_ptr) {
+ uc_priv->bank_name = strdup(label_ptr);
+ if (!uc_priv->bank_name)
+ return -ENOMEM;
+ } else {
+ uc_priv->bank_name = dev->name;
+ }
- if (priv->p_data)
- uc_priv->gpio_count = priv->p_data->ngpio;
+ if (platdata->p_data)
+ uc_priv->gpio_count = platdata->p_data->ngpio;
return 0;
}
static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
{
- struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+ struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
+
+ platdata->base = (phys_addr_t)dev_read_addr(dev);
- priv->base = dev_get_addr(dev);
+ platdata->p_data =
+ (struct zynq_platform_data *)dev_get_driver_data(dev);
return 0;
}
.of_match = zynq_gpio_ids,
.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
.probe = zynq_gpio_probe,
- .priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata),
+ .platdata_auto_alloc_size = sizeof(struct zynq_gpio_platdata),
};
projects / oweals / u-boot.git / blobdiff