Merge git://git.denx.de/u-boot-marvell

[oweals/u-boot.git] / drivers / gpio / rk_gpio.c

diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index 64abcbaa0ac8c654fe1e7342ae783a861a0d5938..3d96678a45a71a0ada12767aeba690ff33fa29fe 100644 (file)
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -1,19 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2015 Google, Inc
  *
  * (C) Copyright 2008-2014 Rockchip Electronics
  * Peter, Software Engineering, <superpeter.cai@gmail.com>.
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <common.h>
 #include <dm.h>
 #include <syscon.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/gpio.h>
 #include <dm/pinctrl.h>
 #include <dt-bindings/clock/rk3288-cru.h>
 
@@ -86,16 +86,58 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
        ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
        if (ret)
                return ret;
-
-       /* If it's not 0, then it is not a GPIO */
-       if (ret)
-               return GPIOF_FUNC;
        is_output = readl(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
 
        return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
 #endif
 }
 
+/* Simple SPL interface to GPIOs */
+#ifdef CONFIG_SPL_BUILD
+
+enum {
+       PULL_NONE_1V8 = 0,
+       PULL_DOWN_1V8 = 1,
+       PULL_UP_1V8 = 3,
+};
+
+int spl_gpio_set_pull(void *vregs, uint gpio, int pull)
+{
+       u32 *regs = vregs;
+       uint val;
+
+       regs += gpio >> GPIO_BANK_SHIFT;
+       gpio &= GPIO_OFFSET_MASK;
+       switch (pull) {
+       case GPIO_PULL_UP:
+               val = PULL_UP_1V8;
+               break;
+       case GPIO_PULL_DOWN:
+               val = PULL_DOWN_1V8;
+               break;
+       case GPIO_PULL_NORMAL:
+       default:
+               val = PULL_NONE_1V8;
+               break;
+       }
+       clrsetbits_le32(regs, 3 << (gpio * 2), val << (gpio * 2));
+
+       return 0;
+}
+
+int spl_gpio_output(void *vregs, uint gpio, int value)
+{
+       struct rockchip_gpio_regs * const regs = vregs;
+
+       clrsetbits_le32(&regs->swport_dr, 1 << gpio, value << gpio);
+
+       /* Set direction */
+       clrsetbits_le32(&regs->swport_ddr, 1 << gpio, 1 << gpio);
+
+       return 0;
+}
+#endif /* CONFIG_SPL_BUILD */
+
 static int rockchip_gpio_probe(struct udevice *dev)
 {
        struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
@@ -103,8 +145,7 @@ static int rockchip_gpio_probe(struct udevice *dev)
        char *end;
        int ret;
 
-       /* This only supports RK3288 at present */
-       priv->regs = (struct rockchip_gpio_regs *)dev_get_addr(dev);
+       priv->regs = dev_read_addr_ptr(dev);
        ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
        if (ret)
                return ret;