Enable FPGA driver for loading bitstream in BIT and BIN format
on Altera Cyclone II device.
+config FPGA_STRATIX10
+ bool "Enable Altera FPGA driver for Stratix 10"
+ depends on TARGET_SOCFPGA_STRATIX10
+ select FPGA_ALTERA
+ help
+ Say Y here to enable the Altera Stratix 10 FPGA specific driver
+
+ This provides common functionality for Altera Stratix 10 devices.
+ Enable FPGA driver for writing bitstream into Altera Stratix10
+ device.
+
config FPGA_XILINX
bool "Enable Xilinx FPGA drivers"
select FPGA
Enable FPGA driver for loading bitstream in BIT and BIN format
on Xilinx Zynq UltraScale+ (ZynqMP) device.
+config FPGA_VERSALPL
+ bool "Enable Xilinx FPGA driver for Versal"
+ depends on FPGA_XILINX
+ help
+ Enable FPGA driver for loading bitstream in PDI format on Xilinx
+ Versal device. PDI is a new programmable device image format for
+ Versal. The bitstream will only be generated as PDI for Versal
+ platform.
+
config FPGA_SPARTAN3
bool "Enable Spartan3 FPGA driver"
+ depends on FPGA_XILINX
help
Enable Spartan3 FPGA driver for loading in BIT format.
+config FPGA_VIRTEX2
+ bool "Enable Xilinx Virtex-II and later FPGA driver"
+ depends on FPGA_XILINX
+ help
+ Enable Virtex-II FPGA driver for loading in BIT format. This driver
+ also supports many newer Xilinx FPGA families.
+
config FPGA_ZYNQPL
bool "Enable Xilinx FPGA for Zynq"
depends on ARCH_ZYNQ