ARM: mvebu: a38x: sync ddr training code with upstream

[oweals/u-boot.git] / drivers / ddr / marvell / a38x / ddr3_training_ip_prv_if.h

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
index 352bc0ce264a44e3e16e3977b0585c2e438f9163..f614d688c915248fa10b2beb753c9c2590a13742 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_prv_if.h
@@ -62,7 +62,7 @@ typedef int (*HWS_TRAINING_IP_PBS_TX_FUNC_PTR)(u32 dev_num);
 typedef int (*HWS_TRAINING_IP_SELECT_CONTROLLER_FUNC_PTR)(
        u32 dev_num, int enable);
 typedef int (*HWS_TRAINING_IP_TOPOLOGY_MAP_LOAD_FUNC_PTR)(
-       u32 dev_num, struct hws_topology_map *topology_map);
+       u32 dev_num, struct mv_ddr_topology_map *tm);
 typedef int (*HWS_TRAINING_IP_STATIC_CONFIG_FUNC_PTR)(
        u32 dev_num, enum hws_ddr_freq frequency,
        enum hws_static_config_type static_config_type, u32 if_id);
@@ -83,16 +83,27 @@ typedef int (*HWS_TRAINING_IP_LOAD_TOPOLOGY)(u32 dev_num, u32 config_num);
 typedef int (*HWS_TRAINING_IP_READ_LEVELING)(u32 dev_num, u32 config_num);
 typedef int (*HWS_TRAINING_IP_WRITE_LEVELING)(u32 dev_num, u32 config_num);
 typedef u32 (*HWS_TRAINING_IP_GET_TEMP)(u8 dev_num);
+typedef u8 (*HWS_TRAINING_IP_GET_RATIO)(u32 freq);
 
 struct hws_tip_config_func_db {
        HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR tip_dunit_mux_select_func;
-       HWS_TIP_DUNIT_REG_READ_FUNC_PTR tip_dunit_read_func;
-       HWS_TIP_DUNIT_REG_WRITE_FUNC_PTR tip_dunit_write_func;
+       void (*mv_ddr_dunit_read)(u32 addr, u32 mask, u32 *data);
+       void (*mv_ddr_dunit_write)(u32 addr, u32 mask, u32 data);
        HWS_TIP_GET_FREQ_CONFIG_INFO tip_get_freq_config_info_func;
        HWS_TIP_GET_DEVICE_INFO tip_get_device_info_func;
        HWS_SET_FREQ_DIVIDER_FUNC_PTR tip_set_freq_divider_func;
        HWS_GET_CS_CONFIG_FUNC_PTR tip_get_cs_config_info;
        HWS_TRAINING_IP_GET_TEMP tip_get_temperature;
+       HWS_TRAINING_IP_GET_RATIO tip_get_clock_ratio;
+       HWS_TRAINING_IP_EXTERNAL_READ_PTR tip_external_read;
+       HWS_TRAINING_IP_EXTERNAL_WRITE_PTR tip_external_write;
+       int (*mv_ddr_phy_read)(enum hws_access_type phy_access,
+                              u32 phy, enum hws_ddr_phy phy_type,
+                              u32 reg_addr, u32 *data);
+       int (*mv_ddr_phy_write)(enum hws_access_type phy_access,
+                               u32 phy, enum hws_ddr_phy phy_type,
+                               u32 reg_addr, u32 data,
+                               enum hws_operation op_type);
 };
 
 int ddr3_tip_init_config_func(u32 dev_num,