ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02

[oweals/u-boot.git] / drivers / ddr / marvell / a38x / ddr3_training_ip.h

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip.h b/drivers/ddr/marvell/a38x/ddr3_training_ip.h
index 0102e6919486a35966cd7d2290da132d2fd30c2c..056c21497c85e7c23685aabf39bbb17be4328287 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_training_ip.h
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip.h
@@ -6,15 +6,10 @@
 #ifndef _DDR3_TRAINING_IP_H_
 #define _DDR3_TRAINING_IP_H_
 
-#include "ddr3_training_ip_def.h"
 #include "ddr_topology_def.h"
-#include "ddr_training_ip_db.h"
 
-#define DDR3_TIP_VERSION_STRING "DDR3 Training Sequence - Ver TIP-1.29."
-
-#define MAX_CS_NUM             4
-#define MAX_TOTAL_BUS_NUM      (MAX_INTERFACE_NUM * MAX_BUS_NUM)
-#define MAX_DQ_NUM             40
+#define TIP_ENG_LOCK   0x02000000
+#define TIP_TX_DLL_RANGE_MAX   64
 
 #define GET_MIN(arg1, arg2)    ((arg1) < (arg2)) ? (arg1) : (arg2)
 #define GET_MAX(arg1, arg2)    ((arg1) < (arg2)) ? (arg2) : (arg1)
@@ -38,11 +33,15 @@
 #define READ_LEVELING_TF_MASK_BIT      0x00010000
 #define WRITE_LEVELING_SUPP_TF_MASK_BIT        0x00020000
 #define DM_PBS_TX_MASK_BIT             0x00040000
+#define RL_DQS_BURST_MASK_BIT          0x00080000
 #define CENTRALIZATION_RX_MASK_BIT     0x00100000
 #define CENTRALIZATION_TX_MASK_BIT     0x00200000
 #define TX_EMPHASIS_MASK_BIT           0x00400000
 #define PER_BIT_READ_LEVELING_TF_MASK_BIT      0x00800000
 #define VREF_CALIBRATION_MASK_BIT      0x01000000
+#define WRITE_LEVELING_LF_MASK_BIT     0x02000000
+
+/* DDR4 Specific Training Mask bits */
 
 enum hws_result {
        TEST_FAILED = 0,
@@ -79,6 +78,7 @@ enum auto_tune_stage {
        TX_EMPHASIS,
        LOAD_PATTERN_HIGH,
        PER_BIT_READ_LEVELING_TF,
+       WRITE_LEVELING_LF,
        MAX_STAGE_LIMIT
 };
 
@@ -108,40 +108,11 @@ struct pattern_info {
        u8 pattern_len;
 };
 
-/* CL value for each frequency */
-struct cl_val_per_freq {
-       u8 cl_val[DDR_FREQ_LIMIT];
-};
-
 struct cs_element {
        u8 cs_num;
        u8 num_of_cs;
 };
 
-struct mode_info {
-       /* 32 bits representing MRS bits */
-       u32 reg_mr0[MAX_INTERFACE_NUM];
-       u32 reg_mr1[MAX_INTERFACE_NUM];
-       u32 reg_mr2[MAX_INTERFACE_NUM];
-       u32 reg_m_r3[MAX_INTERFACE_NUM];
-       /*
-        * Each element in array represent read_data_sample register delay for
-        * a specific interface.
-        * Each register, 4 bits[0+CS*8 to 4+CS*8] represent Number of DDR
-        * cycles from read command until data is ready to be fetched from
-        * the PHY, when accessing CS.
-        */
-       u32 read_data_sample[MAX_INTERFACE_NUM];
-       /*
-        * Each element in array represent read_data_sample register delay for
-        * a specific interface.
-        * Each register, 4 bits[0+CS*8 to 4+CS*8] represent the total delay
-        * from read command until opening the read mask, when accessing CS.
-        * This field defines the delay in DDR cycles granularity.
-        */
-       u32 read_data_ready[MAX_INTERFACE_NUM];
-};
-
 struct hws_tip_freq_config_info {
        u8 is_supported;
        u8 bw_per_freq;
@@ -167,11 +138,9 @@ int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
 int hws_ddr3_tip_init_controller(u32 dev_num,
                                 struct init_cntr_param *init_cntr_prm);
 int hws_ddr3_tip_load_topology_map(u32 dev_num,
-                                  struct hws_topology_map *topology);
+                                  struct mv_ddr_topology_map *topology);
 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
-int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
 int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
 u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
 u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
-
 #endif /* _DDR3_TRAINING_IP_H_ */