Merge branch 'master' of git://git.denx.de/u-boot-sh

[oweals/u-boot.git] / drivers / ddr / fsl / util.c

diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 7a22aa398865655b0cb8f8ca8069b648bfb1c463..664081b1b8369ae57fb7e32634ee2a839711c9d1 100644 (file)
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -43,9 +43,9 @@ u32 fsl_ddr_get_version(void)
  * propagation, compute a suitably rounded mclk_ps to compute
  * a working memory controller configuration.
  */
-unsigned int get_memory_clk_period_ps(void)
+unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
 {
-       unsigned int data_rate = get_ddr_freq(0);
+       unsigned int data_rate = get_ddr_freq(ctrl_num);
        unsigned int result;
 
        /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
@@ -59,10 +59,10 @@ unsigned int get_memory_clk_period_ps(void)
 }
 
 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
-unsigned int picos_to_mclk(unsigned int picos)
+unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
 {
        unsigned long long clks, clks_rem;
-       unsigned long data_rate = get_ddr_freq(0);
+       unsigned long data_rate = get_ddr_freq(ctrl_num);
 
        /* Short circuit for zero picos */
        if (!picos)
@@ -88,9 +88,9 @@ unsigned int picos_to_mclk(unsigned int picos)
        return (unsigned int) clks;
 }
 
-unsigned int mclk_to_picos(unsigned int mclk)
+unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
 {
-       return get_memory_clk_period_ps() * mclk;
+       return get_memory_clk_period_ps(ctrl_num) * mclk;
 }
 
 #ifdef CONFIG_PPC
@@ -149,7 +149,7 @@ u32 fsl_ddr_get_intl3r(void)
        return val;
 }
 
-void board_add_ram_info(int use_default)
+void print_ddr_info(unsigned int start_ctrl)
 {
        struct ccsr_ddr __iomem *ddr =
                (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
@@ -164,17 +164,25 @@ void board_add_ram_info(int use_default)
        int cas_lat;
 
 #if CONFIG_NUM_DDR_CONTROLLERS >= 2
-       if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+       if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
+           (start_ctrl == 1)) {
                ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
                sdram_cfg = ddr_in32(&ddr->sdram_cfg);
        }
 #endif
 #if CONFIG_NUM_DDR_CONTROLLERS >= 3
-       if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+       if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
+           (start_ctrl == 2)) {
                ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
                sdram_cfg = ddr_in32(&ddr->sdram_cfg);
        }
 #endif
+
+       if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+               puts(" (DDR not enabled)\n");
+               return;
+       }
+
        puts(" (DDR");
        switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
                SDRAM_CFG_SDRAM_TYPE_SHIFT) {
@@ -241,7 +249,7 @@ void board_add_ram_info(int use_default)
 #endif
 #endif
 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
-       if (cs0_config & 0x20000000) {
+       if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
                puts("\n");
                puts("       DDR Controller Interleaving Mode: ");
 
@@ -290,3 +298,68 @@ void board_add_ram_info(int use_default)
                }
        }
 }
+
+void __weak detail_board_ddr_info(void)
+{
+       print_ddr_info(0);
+}
+
+void board_add_ram_info(int use_default)
+{
+       detail_board_ddr_info();
+}
+
+#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
+#define DDRC_DEBUG20_INIT_DONE 0x80000000
+#define DDRC_DEBUG2_RF         0x00000040
+void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
+                                unsigned int last_ctrl)
+{
+       unsigned int i;
+       u32 ddrc_debug20;
+       u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
+       u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
+       struct ccsr_ddr __iomem *ddr;
+
+       for (i = first_ctrl; i <= last_ctrl; i++) {
+               switch (i) {
+               case 0:
+                       ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+                       break;
+#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+               case 1:
+                       ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+                       break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+               case 2:
+                       ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+                       break;
+#endif
+#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+               case 3:
+                       ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
+                       break;
+#endif
+               default:
+                       printf("%s unexpected ctrl = %u\n", __func__, i);
+                       return;
+               }
+               ddrc_debug20 = ddr_in32(&ddr->debug[19]);
+               ddrc_debug2_p[i] = &ddr->debug[1];
+               while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
+                       /* keep polling until DDRC init is done */
+                       udelay(100);
+                       ddrc_debug20 = ddr_in32(&ddr->debug[19]);
+               }
+               ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
+       }
+       /*
+        * Sync refresh
+        * This is put together to make sure the refresh reqeusts are sent
+        * closely to each other.
+        */
+       for (i = first_ctrl; i <= last_ctrl; i++)
+               ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
+}
+#endif /* CONFIG_FSL_DDR_SYNC_REFRESH */