ddr: altera: Clean up sdr_find_window_centre() part 2

[oweals/u-boot.git] / drivers / ddr / fsl / options.c

diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 31cc2bfecd2db8401945fd79fa2bf0934b92ba77..3c09c643febd87085957a865a237f30381d5c674 100644 (file)
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -499,7 +499,7 @@ static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
        return 0;
 }
 
-unsigned int populate_memctl_options(int all_dimms_registered,
+unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
                        memctl_options_t *popts,
                        dimm_params_t *pdimm,
                        unsigned int ctrl_num)
@@ -640,7 +640,7 @@ unsigned int populate_memctl_options(int all_dimms_registered,
        popts->ba_intlv_ctl = 0;
 
        /* Memory Organization Parameters */
-       popts->registered_dimm_en = all_dimms_registered;
+       popts->registered_dimm_en = common_dimm->all_dimms_registered;
 
        /* Operational Mode Paramters */
 
@@ -728,11 +728,16 @@ unsigned int populate_memctl_options(int all_dimms_registered,
 
        /* Choose ddr controller address mirror mode */
 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
-       popts->mirrored_dimm = pdimm[0].mirrored_dimm;
+       for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+               if (pdimm[i].n_ranks) {
+                       popts->mirrored_dimm = pdimm[i].mirrored_dimm;
+                       break;
+               }
+       }
 #endif
 
        /* Global Timing Parameters. */
-       debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
+       debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
 
        /* Pick a caslat override. */
        popts->cas_latency_override = 0;
@@ -773,13 +778,11 @@ unsigned int populate_memctl_options(int all_dimms_registered,
         * Set this to 0 for global auto precharge
         * The value of 0x100 has been used for DDR1, DDR2, DDR3.
         * It is not wrong. Any value should be OK. The performance depends on
-        * applications. There is no one good value for all.
+        * applications. There is no one good value for all. One way to set
+        * is to use 1/4 of refint value.
         */
-       popts->bstopre = 0x100;
-
-       /* Minimum CKE pulse width -- tCKE(MIN) */
-       popts->tcke_clock_pulse_width_ps
-               = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
+       popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
+                        >> 2;
 
        /*
         * Window for four activates -- tFAW
@@ -789,7 +792,7 @@ unsigned int populate_memctl_options(int all_dimms_registered,
         * FIXME: width, was considering looking at pdimm->primary_sdram_width
         */
 #if defined(CONFIG_SYS_FSL_DDR1)
-       popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
+       popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
 
 #elif defined(CONFIG_SYS_FSL_DDR2)
        /*
@@ -1040,7 +1043,7 @@ done:
        if (pdimm[0].n_ranks == 4)
                popts->quad_rank_present = 1;
 
-       ddr_freq = get_ddr_freq(0) / 1000000;
+       ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
        if (popts->registered_dimm_en) {
                popts->rcw_override = 1;
                popts->rcw_1 = 0x000a5a00;