Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga

[oweals/u-boot.git] / drivers / ddr / fsl / options.c

diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 6d098d1fa2f5023e3b4cd3f77efe3283ef78def8..3b30fa284c49fc2a2194d5f0a19fc7565bcc4bdb 100644 (file)
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -728,11 +728,16 @@ unsigned int populate_memctl_options(int all_dimms_registered,
 
        /* Choose ddr controller address mirror mode */
 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
-       popts->mirrored_dimm = pdimm[0].mirrored_dimm;
+       for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+               if (pdimm[i].n_ranks) {
+                       popts->mirrored_dimm = pdimm[i].mirrored_dimm;
+                       break;
+               }
+       }
 #endif
 
        /* Global Timing Parameters. */
-       debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
+       debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
 
        /* Pick a caslat override. */
        popts->cas_latency_override = 0;
@@ -785,7 +790,7 @@ unsigned int populate_memctl_options(int all_dimms_registered,
         * FIXME: width, was considering looking at pdimm->primary_sdram_width
         */
 #if defined(CONFIG_SYS_FSL_DDR1)
-       popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
+       popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
 
 #elif defined(CONFIG_SYS_FSL_DDR2)
        /*
@@ -1036,7 +1041,7 @@ done:
        if (pdimm[0].n_ranks == 4)
                popts->quad_rank_present = 1;
 
-       ddr_freq = get_ddr_freq(0) / 1000000;
+       ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
        if (popts->registered_dimm_en) {
                popts->rcw_override = 1;
                popts->rcw_1 = 0x000a5a00;