Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[oweals/u-boot.git] / drivers / ddr / fsl / main.c

diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 6f291ebc03222c7a72f18a417f73554412b796ef..b72b24290ec911acadfa9186062fbd08c72c7eac 100644 (file)
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -450,7 +450,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
                                        &(pinfo->spd_installed_dimms[i][j]);
                                dimm_params_t *pdimm =
                                        &(pinfo->dimm_params[i][j]);
-                               retval = compute_dimm_parameters(spd, pdimm, i);
+                               retval = compute_dimm_parameters(
+                                                       i, spd, pdimm, j);
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
                                if (!i && !j && retval) {
                                        printf("SPD error on controller %d! "
@@ -507,10 +508,11 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
                for (i = first_ctrl; i <= last_ctrl; i++) {
                        debug("Computing lowest common DIMM"
                                " parameters for memctl=%u\n", i);
-                       compute_lowest_common_dimm_parameters(
-                               pinfo->dimm_params[i],
-                               &timing_params[i],
-                               CONFIG_DIMM_SLOTS_PER_CTLR);
+                       compute_lowest_common_dimm_parameters
+                               (i,
+                                pinfo->dimm_params[i],
+                                &timing_params[i],
+                                CONFIG_DIMM_SLOTS_PER_CTLR);
                }
 
        case STEP_GATHER_OPTS:
@@ -562,12 +564,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
                                continue;
                        }
 
-                       compute_fsl_memctl_config_regs(
-                                       &pinfo->memctl_opts[i],
-                                       &ddr_reg[i], &timing_params[i],
-                                       pinfo->dimm_params[i],
-                                       dbw_capacity_adjust[i],
-                                       size_only);
+                       compute_fsl_memctl_config_regs
+                               (i,
+                                &pinfo->memctl_opts[i],
+                                &ddr_reg[i], &timing_params[i],
+                                pinfo->dimm_params[i],
+                                dbw_capacity_adjust[i],
+                                size_only);
                }
 
        default:
@@ -689,6 +692,10 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
                }
        }
 
+#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
+       fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
+#endif
+
 #ifdef CONFIG_PPC
        /* program LAWs */
        for (i = first_ctrl; i <= last_ctrl; i++) {