Merge git://git.denx.de/u-boot-nand-flash

[oweals/u-boot.git] / drivers / ddr / fsl / fsl_ddr_gen4.c

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 608810d4e29cb09be3193869101d956293f48464..d37e2474c91d0b8a2a02fb041865f5f52e14f525 100644 (file)
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -56,7 +56,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
        u32 *vref_seq = vref_seq1;
 #endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \
+       defined(CONFIG_SYS_FSL_ERRATUM_A010165)
        ulong ddr_freq;
        u32 tmp;
 #endif
@@ -205,12 +206,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
        /* part 1 of 2 */
-       if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
-               ddr_out32(&ddr->ddr_sdram_rcw_2,
-                         regs->ddr_sdram_rcw_2 & ~0x0f000000);
+       if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+               if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
+                       ddr_out32(&ddr->ddr_sdram_rcw_2,
+                                 regs->ddr_sdram_rcw_2 & ~0x0f000000);
+               }
+               ddr_out32(&ddr->err_disable, regs->err_disable |
+                         DDR_ERR_DISABLE_APED);
        }
-
-       ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
 #else
        ddr_out32(&ddr->err_disable, regs->err_disable);
 #endif
@@ -240,8 +243,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                /* Disable DRAM VRef training */
                ddr_out32(&ddr->ddr_cdr2,
                          regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
-               /* Disable deskew */
-               ddr_out32(&ddr->debug[28], 0x400);
+               /* disable transmit bit deskew */
+               temp32 = ddr_in32(&ddr->debug[28]);
+               temp32 |= DDR_TX_BD_DIS;
+               ddr_out32(&ddr->debug[28], temp32);
                /* Disable D_INIT */
                ddr_out32(&ddr->sdram_cfg_2,
                          regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
@@ -249,6 +254,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        }
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009801
+       temp32 = ddr_in32(&ddr->debug[25]);
+       temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
+       temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
+       ddr_out32(&ddr->debug[25], temp32);
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
        ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
        tmp = ddr_in32(&ddr->debug[28]);
@@ -262,6 +274,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010165
+       ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+       if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
+               tmp = ddr_in32(&ddr->debug[28]);
+               ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
+       }
+#endif
        /*
         * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
         * deasserted. Clocks start when any chip select is enabled and clock
@@ -358,7 +377,9 @@ step2:
                        debug("MR6 = 0x%08x\n", temp32);
                }
                ddr_out32(&ddr->sdram_md_cntl, 0);
-               ddr_out32(&ddr->debug[28], 0);          /* Enable deskew */
+               temp32 = ddr_in32(&ddr->debug[28]);
+               temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
+               ddr_out32(&ddr->debug[28], temp32);
                ddr_out32(&ddr->debug[1], 0x400);       /* restart deskew */
                /* wait for idle */
                timeout = 40;
@@ -376,22 +397,24 @@ step2:
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
-               /* if it's RDIMM */
-               if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
-                       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-                               if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
-                                       continue;
-                               set_wait_for_bits_clear(&ddr->sdram_md_cntl,
-                                                       MD_CNTL_MD_EN |
-                                                       MD_CNTL_CS_SEL(i) |
-                                                       0x070000ed,
-                                                       MD_CNTL_MD_EN);
-                               udelay(1);
+               if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+                       /* if it's RDIMM */
+                       if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+                               for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+                                       if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+                                               continue;
+                                       set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+                                                               MD_CNTL_MD_EN |
+                                                               MD_CNTL_CS_SEL(i) |
+                                                               0x070000ed,
+                                                               MD_CNTL_MD_EN);
+                                       udelay(1);
+                               }
                        }
-               }
 
-               ddr_out32(&ddr->err_disable,
-                         regs->err_disable & ~DDR_ERR_DISABLE_APED);
+                       ddr_out32(&ddr->err_disable,
+                                 regs->err_disable & ~DDR_ERR_DISABLE_APED);
+               }
 #endif
        }
 #endif