acpi: Specify U-Boot include path for ASL files

[oweals/u-boot.git] / drivers / ddr / fsl / fsl_ddr_gen4.c

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 3fca5c2684bda5025a066bbe5d1751aab43d9b33..608810d4e29cb09be3193869101d956293f48464 100644 (file)
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -12,7 +12,8 @@
 #include <fsl_ddr.h>
 #include <fsl_errata.h>
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
+       defined(CONFIG_SYS_FSL_ERRATUM_A009803)
 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
 {
        int timeout = 1000;
@@ -24,9 +25,9 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
                timeout--;
        }
        if (timeout <= 0)
-               puts("Error: A007865 wait for clear timeout.\n");
+               puts("Error: wait for clear timeout.\n");
 }
-#endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
+#endif
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
@@ -55,6 +56,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
        u32 *vref_seq = vref_seq1;
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+       ulong ddr_freq;
+       u32 tmp;
+#endif
 #ifdef CONFIG_FSL_DDR_BIST
        u32 mtcr, err_detect, err_sbe;
        u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
@@ -151,7 +156,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
        ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
        ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
+       ddr_out32(&ddr->sdram_interval,
+                 regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
+#else
        ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+#endif
        ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
        ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 #ifndef CONFIG_SYS_FSL_DDR_EMU
@@ -192,7 +202,18 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
                ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
        }
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
+       /* part 1 of 2 */
+       if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
+               ddr_out32(&ddr->ddr_sdram_rcw_2,
+                         regs->ddr_sdram_rcw_2 & ~0x0f000000);
+       }
+
+       ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
+#else
        ddr_out32(&ddr->err_disable, regs->err_disable);
+#endif
        ddr_out32(&ddr->err_int_en, regs->err_int_en);
        for (i = 0; i < 32; i++) {
                if (regs->debug[i]) {
@@ -227,6 +248,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                ddr_out32(&ddr->debug[25], 0x9000);
        }
 #endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+       ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+       tmp = ddr_in32(&ddr->debug[28]);
+       if (ddr_freq <= 1333)
+               ddr_out32(&ddr->debug[28], tmp | 0x0080006a);
+       else if (ddr_freq <= 1600)
+               ddr_out32(&ddr->debug[28], tmp | 0x0070006f);
+       else if (ddr_freq <= 1867)
+               ddr_out32(&ddr->debug[28], tmp | 0x00700076);
+       else if (ddr_freq <= 2133)
+               ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
+#endif
+
        /*
         * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
         * deasserted. Clocks start when any chip select is enabled and clock
@@ -274,7 +309,8 @@ step2:
        mb();
        isb();
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
+#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
+       defined(CONFIG_SYS_FSL_ERRATUM_A009803)
        /* Part 2 of 2 */
        /* This erraum only applies to verion 5.2.0 */
        if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
@@ -290,6 +326,7 @@ step2:
                               ctrl_num, ddr_in32(&ddr->debug[1]));
                }
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008511
                /* The vref setting sequence is different for range 2 */
                if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
                        vref_seq = vref_seq2;
@@ -336,9 +373,29 @@ step2:
                }
                /* Restore D_INIT */
                ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
-       }
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009803
+               /* if it's RDIMM */
+               if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+                       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+                               if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+                                       continue;
+                               set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+                                                       MD_CNTL_MD_EN |
+                                                       MD_CNTL_CS_SEL(i) |
+                                                       0x070000ed,
+                                                       MD_CNTL_MD_EN);
+                               udelay(1);
+                       }
+               }
+
+               ddr_out32(&ddr->err_disable,
+                         regs->err_disable & ~DDR_ERR_DISABLE_APED);
+#endif
+       }
+#endif
+
        total_gb_size_per_controller = 0;
        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
                if (!(regs->cs[i].config & 0x80000000))
@@ -379,6 +436,11 @@ step2:
 
        if (timeout <= 0)
                printf("Waiting for D_INIT timeout. Memory may not work.\n");
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
+       ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
+#endif
+
 #ifdef CONFIG_DEEP_SLEEP
        if (is_warm_boot()) {
                /* exit self-refresh */