ddr: altera: sdram: Minor cleanup in sdram_set_rule()
[oweals/u-boot.git] / drivers / ddr / altera / sequencer.h
index 0aa9579270f5349a1183ecc09926f5707e961fc7..3e4152f69f8a033310e5668fd39769a47af804f6 100644 (file)
 #define SCC_MGR_HHP_RFILE_OFFSET               0x0B00
 #define SCC_MGR_AFI_CAL_INIT_OFFSET            0x0D00
 
-#define SDR_PHYGRP_SCCGRP_ADDRESS              0x0
-#define SDR_PHYGRP_PHYMGRGRP_ADDRESS           0x1000
-#define SDR_PHYGRP_RWMGRGRP_ADDRESS            0x2000
-#define SDR_PHYGRP_DATAMGRGRP_ADDRESS          0x4000
-#define SDR_PHYGRP_REGFILEGRP_ADDRESS          0x4800
-
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
+#define SDR_PHYGRP_SCCGRP_ADDRESS              (SOCFPGA_SDR_ADDRESS | 0x0)
+#define SDR_PHYGRP_PHYMGRGRP_ADDRESS           (SOCFPGA_SDR_ADDRESS | 0x1000)
+#define SDR_PHYGRP_RWMGRGRP_ADDRESS            (SOCFPGA_SDR_ADDRESS | 0x2000)
+#define SDR_PHYGRP_DATAMGRGRP_ADDRESS          (SOCFPGA_SDR_ADDRESS | 0x4000)
+#define SDR_PHYGRP_REGFILEGRP_ADDRESS          (SOCFPGA_SDR_ADDRESS | 0x4800)
 
 #define PHY_MGR_CAL_RESET              (0)
 #define PHY_MGR_CAL_SUCCESS            (1)
@@ -246,10 +242,6 @@ struct gbl_type {
 
        uint32_t curr_read_lat;
 
-       /* current write latency */
-
-       uint32_t curr_write_lat;
-
        /* error code */
 
        uint32_t error_substage;