ddr: altera: Clean up sdr_*_phase() part 9

[oweals/u-boot.git] / drivers / ddr / altera / sequencer.h

diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 7591d407281f79936efcd7ae50676f928c4a1109..3e4152f69f8a033310e5668fd39769a47af804f6 100644 (file)
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -99,10 +99,6 @@
 #define SDR_PHYGRP_DATAMGRGRP_ADDRESS          (SOCFPGA_SDR_ADDRESS | 0x4000)
 #define SDR_PHYGRP_REGFILEGRP_ADDRESS          (SOCFPGA_SDR_ADDRESS | 0x4800)
 
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
-
 #define PHY_MGR_CAL_RESET              (0)
 #define PHY_MGR_CAL_SUCCESS            (1)
 #define PHY_MGR_CAL_FAIL               (2)
@@ -246,10 +242,6 @@ struct gbl_type {
 
        uint32_t curr_read_lat;
 
-       /* current write latency */
-
-       uint32_t curr_write_lat;
-
        /* error code */
 
        uint32_t error_substage;