#include <asm/arch/sdram.h>
#include <errno.h>
#include "sequencer.h"
-#include "sequencer_auto.h"
-#include "sequencer_auto_ac_init.h"
-#include "sequencer_auto_inst_init.h"
-#include "sequencer_defines.h"
+
+/*
+ * FIXME: This path is temporary until the SDRAM driver gets
+ * a proper thorough cleanup.
+ */
+#include "../../../board/altera/socfpga/qts/sequencer_auto.h"
+#include "../../../board/altera/socfpga/qts/sequencer_defines.h"
static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
(struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+const struct socfpga_sdram_rw_mgr_config *rwcfg;
+const struct socfpga_sdram_io_config *iocfg;
+const struct socfpga_sdram_misc_config *misccfg;
+
#define DELTA_D 1
/*
struct gbl_type *gbl;
struct param_type *param;
-uint32_t curr_shadow_reg;
-
-static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
- uint32_t write_group, uint32_t use_dm,
- uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
static void set_failing_group_stage(uint32_t group, uint32_t stage,
uint32_t substage)
if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
return;
- ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ ratio = rwcfg->mem_dq_per_read_dqs /
+ rwcfg->mem_virtual_groups_per_read_dqs;
param->read_correct_mask_vg = (1 << ratio) - 1;
param->write_correct_mask_vg = (1 << ratio) - 1;
- param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
- param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
- ratio = RW_MGR_MEM_DATA_WIDTH /
- RW_MGR_MEM_DATA_MASK_WIDTH;
- param->dm_correct_mask = (1 << ratio) - 1;
+ param->read_correct_mask = (1 << rwcfg->mem_dq_per_read_dqs) - 1;
+ param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1;
}
/**
odt_mask_0 = 0x0;
odt_mask_1 = 0x0;
} else { /* RW_MGR_ODT_MODE_READ_WRITE */
- switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
+ switch (rwcfg->mem_number_of_ranks) {
case 1: /* 1 Rank */
/* Read: ODT = 0 ; Write: ODT = 1 */
odt_mask_0 = 0x0;
odt_mask_1 = 0x1;
break;
case 2: /* 2 Ranks */
- if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
+ if (rwcfg->mem_number_of_cs_per_dimm == 1) {
/*
* - Dual-Slot , Single-Rank (1 CS per DIMM)
* OR
static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
{
- scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
delay);
}
static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
{
- scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
delay);
}
static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
{
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
- RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
+ rwcfg->mem_dq_per_write_dqs + 1 + dm,
delay);
}
{
u32 r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_set(off, grp, val);
*/
static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
{
- const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const int ratio = rwcfg->mem_if_read_dqs_width /
+ rwcfg->mem_if_write_dqs_width;
const int base = write_group * ratio;
int i;
/*
* USER Zero all DQS config settings, across all groups and all
* shadow registers
*/
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
/*
* The phases actually don't exist on a per-rank basis,
* but there's no harm updating them several times, so
* let's keep the code simple.
*/
- scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
+ scc_mgr_set_dqs_bus_in_delay(i, iocfg->dqs_in_reserve);
scc_mgr_set_dqs_en_phase(i, 0);
scc_mgr_set_dqs_en_delay(i, 0);
}
- for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) {
scc_mgr_set_dqdqs_output_phase(i, 0);
/* Arria V/Cyclone V don't have out2. */
- scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
+ scc_mgr_set_oct_out1_delay(i, iocfg->dqs_out_reserve);
}
}
*/
static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
{
- const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const int ratio = rwcfg->mem_if_read_dqs_width /
+ rwcfg->mem_if_write_dqs_width;
const int base = write_group * ratio;
int i;
/*
{
int i, r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
/* Zero all DQ config settings. */
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
scc_mgr_set_dq_out1_delay(i, 0);
if (!out_only)
scc_mgr_set_dq_in_delay(i, 0);
scc_mgr_set_dqs_io_in_delay(0);
/* Arria V/Cyclone V don't have out2. */
- scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
- scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
+ scc_mgr_set_dqs_out1_delay(iocfg->dqs_out_reserve);
+ scc_mgr_set_oct_out1_delay(write_group, iocfg->dqs_out_reserve);
scc_mgr_load_dqs_for_write_group(write_group);
/* Multicast to all DQS IO enables (only 1 in total). */
{
uint32_t i, p;
- for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
+ for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) {
scc_mgr_set_dq_in_delay(p, delay);
scc_mgr_load_dq(p);
}
{
int i;
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
scc_mgr_set_dq_out1_delay(i, delay);
scc_mgr_load_dq(i);
}
u32 i, new_delay;
/* DQ shift */
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++)
scc_mgr_load_dq(i);
/* DM shift */
/* DQS shift */
new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
- if (new_delay > IO_IO_OUT2_DELAY_MAX) {
+ if (new_delay > iocfg->io_out2_delay_max) {
debug_cond(DLEVEL == 1,
"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
__func__, __LINE__, write_group, delay, new_delay,
- IO_IO_OUT2_DELAY_MAX,
- new_delay - IO_IO_OUT2_DELAY_MAX);
- new_delay -= IO_IO_OUT2_DELAY_MAX;
+ iocfg->io_out2_delay_max,
+ new_delay - iocfg->io_out2_delay_max);
+ new_delay -= iocfg->io_out2_delay_max;
scc_mgr_set_dqs_out1_delay(new_delay);
}
/* OCT shift */
new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
- if (new_delay > IO_IO_OUT2_DELAY_MAX) {
+ if (new_delay > iocfg->io_out2_delay_max) {
debug_cond(DLEVEL == 1,
"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
__func__, __LINE__, write_group, delay,
- new_delay, IO_IO_OUT2_DELAY_MAX,
- new_delay - IO_IO_OUT2_DELAY_MAX);
- new_delay -= IO_IO_OUT2_DELAY_MAX;
+ new_delay, iocfg->io_out2_delay_max,
+ new_delay - iocfg->io_out2_delay_max);
+ new_delay -= iocfg->io_out2_delay_max;
scc_mgr_set_oct_out1_delay(write_group, new_delay);
}
{
int r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_apply_group_all_out_delay_add(write_group, delay);
writel(0, &sdr_scc_mgr->update);
* we always jump.
*/
writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
}
-/*
- * should always use constants as argument to ensure all computations are
- * performed at compile time
+/**
+ * delay_for_n_mem_clocks() - Delay for N memory clocks
+ * @clocks: Length of the delay
+ *
+ * Delay for N memory clocks.
*/
-static void delay_for_n_mem_clocks(const uint32_t clocks)
+static void delay_for_n_mem_clocks(const u32 clocks)
{
- uint32_t afi_clocks;
- uint8_t inner = 0;
- uint8_t outer = 0;
- uint16_t c_loop = 0;
+ u32 afi_clocks;
+ u16 c_loop;
+ u8 inner;
+ u8 outer;
debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
-
- afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
- /* scale (rounding up) to get afi clocks */
+ /* Scale (rounding up) to get afi clocks. */
+ afi_clocks = DIV_ROUND_UP(clocks, AFI_RATE_RATIO);
+ if (afi_clocks) /* Temporary underflow protection */
+ afi_clocks--;
/*
- * Note, we don't bother accounting for being off a little bit
- * because of a few extra instructions in outer loops
- * Note, the loops have a test at the end, and do the test before
- * the decrement, and so always perform the loop
+ * Note, we don't bother accounting for being off a little
+ * bit because of a few extra instructions in outer loops.
+ * Note, the loops have a test at the end, and do the test
+ * before the decrement, and so always perform the loop
* 1 time more than the counter value
*/
- if (afi_clocks == 0) {
- ;
- } else if (afi_clocks <= 0x100) {
- inner = afi_clocks-1;
- outer = 0;
- c_loop = 0;
- } else if (afi_clocks <= 0x10000) {
- inner = 0xff;
- outer = (afi_clocks-1) >> 8;
- c_loop = 0;
- } else {
- inner = 0xff;
- outer = 0xff;
- c_loop = (afi_clocks-1) >> 16;
- }
+ c_loop = afi_clocks >> 16;
+ outer = c_loop ? 0xff : (afi_clocks >> 8);
+ inner = outer ? 0xff : afi_clocks;
/*
* rom instructions are structured as follows:
* and sequencer rom and keeps the delays more accurate and reduces
* overhead
*/
- if (afi_clocks <= 0x100) {
+ if (afi_clocks < 0x100) {
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
&sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_IDLE_LOOP1,
+ writel(rwcfg->idle_loop1,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
&sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_IDLE_LOOP2,
+ writel(rwcfg->idle_loop2,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_IDLE_LOOP2,
+ writel(rwcfg->idle_loop2,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- /* hack to get around compiler not being smart enough */
- if (afi_clocks <= 0x10000) {
- /* only need to run once */
- writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RUN_SINGLE_GROUP_OFFSET);
- } else {
- do {
- writel(RW_MGR_IDLE_LOOP2,
- SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RUN_SINGLE_GROUP_OFFSET);
- } while (c_loop-- != 0);
- }
+ do {
+ writel(rwcfg->idle_loop2,
+ SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
+ } while (c_loop-- != 0);
}
debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
}
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
u32 r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
- if (param->skip_ranks[r]) {
- /* request to skip the rank */
- continue;
- }
-
+ for (r = 0; r < rwcfg->mem_number_of_ranks; r++) {
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
/* precharge all banks ... */
if (precharge)
- writel(RW_MGR_PRECHARGE_ALL, grpaddr);
+ writel(rwcfg->precharge_all, grpaddr);
/*
* USER Use Mirror-ed commands for odd ranks if address
* mirrorring is on
*/
- if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
+ if ((rwcfg->mem_address_mirroring >> r) & 0x1) {
set_jump_as_return();
- writel(RW_MGR_MRS2_MIRR, grpaddr);
+ writel(rwcfg->mrs2_mirr, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, grpaddr);
+ writel(rwcfg->mrs3_mirr, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, grpaddr);
+ writel(rwcfg->mrs1_mirr, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
writel(fin1, grpaddr);
} else {
set_jump_as_return();
- writel(RW_MGR_MRS2, grpaddr);
+ writel(rwcfg->mrs2, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3, grpaddr);
+ writel(rwcfg->mrs3, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1, grpaddr);
+ writel(rwcfg->mrs1, grpaddr);
set_jump_as_return();
writel(fin2, grpaddr);
}
continue;
set_jump_as_return();
- writel(RW_MGR_ZQCL, grpaddr);
+ writel(rwcfg->zqcl, grpaddr);
/* tZQinit = tDLLK = 512 ck cycles */
delay_for_n_mem_clocks(512);
* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
* b = 6A
*/
- rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
- SEQ_TINIT_CNTR2_VAL,
- RW_MGR_INIT_RESET_0_CKE_0);
+ rw_mgr_mem_init_load_regs(TINIT_CNTR0_VAL, TINIT_CNTR1_VAL,
+ TINIT_CNTR2_VAL,
+ rwcfg->init_reset_0_cke_0);
/* Indicate that memory is stable. */
writel(1, &phy_mgr_cfg->reset_mem_stbl);
* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
* b = FF
*/
- rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
- SEQ_TRESET_CNTR2_VAL,
- RW_MGR_INIT_RESET_1_CKE_0);
+ rw_mgr_mem_init_load_regs(TRESET_CNTR0_VAL, TRESET_CNTR1_VAL,
+ TRESET_CNTR2_VAL,
+ rwcfg->init_reset_1_cke_0);
/* Bring up clock enable. */
/* tXRP < 250 ck cycles */
delay_for_n_mem_clocks(250);
- rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
+ rw_mgr_mem_load_user(rwcfg->mrs0_dll_reset_mirr, rwcfg->mrs0_dll_reset,
0);
}
-/*
- * At the end of calibration we have to program the user settings in, and
- * USER hand off the memory to the user.
+/**
+ * rw_mgr_mem_handoff() - Hand off the memory to user
+ *
+ * At the end of calibration we have to program the user settings in
+ * and hand off the memory to the user.
*/
static void rw_mgr_mem_handoff(void)
{
- rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
+ rw_mgr_mem_load_user(rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1);
+ /*
+ * Need to wait tMOD (12CK or 15ns) time before issuing other
+ * commands, but we will have plenty of NIOS cycles before actual
+ * handoff so its okay.
+ */
+}
+
+/**
+ * rw_mgr_mem_calibrate_write_test_issue() - Issue write test command
+ * @group: Write Group
+ * @use_dm: Use DM
+ *
+ * Issue write test command. Two variants are provided, one that just tests
+ * a write pattern and another that tests datamask functionality.
+ */
+static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
+ u32 test_dm)
+{
+ const u32 quick_write_mode =
+ (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) &&
+ ENABLE_SUPER_QUICK_CALIBRATION;
+ u32 mcc_instruction;
+ u32 rw_wl_nop_cycles;
+
+ /*
+ * Set counter and jump addresses for the right
+ * number of NOP cycles.
+ * The number of supported NOP cycles can range from -1 to infinity
+ * Three different cases are handled:
+ *
+ * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
+ * mechanism will be used to insert the right number of NOPs
+ *
+ * 2. For a number of NOP cycles equals to 0, the micro-instruction
+ * issuing the write command will jump straight to the
+ * micro-instruction that turns on DQS (for DDRx), or outputs write
+ * data (for RLD), skipping
+ * the NOP micro-instruction all together
+ *
+ * 3. A number of NOP cycles equal to -1 indicates that DQS must be
+ * turned on in the same micro-instruction that issues the write
+ * command. Then we need
+ * to directly jump to the micro-instruction that sends out the data
+ *
+ * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
+ * (2 and 3). One jump-counter (0) is used to perform multiple
+ * write-read operations.
+ * one counter left to issue this command in "multiple-group" mode
+ */
+
+ rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
+
+ if (rw_wl_nop_cycles == -1) {
+ /*
+ * CNTR 2 - We want to execute the special write operation that
+ * turns on DQS right away and then skip directly to the
+ * instruction that sends out the data. We set the counter to a
+ * large number so that the jump is always taken.
+ */
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
+
+ /* CNTR 3 - Not used */
+ if (test_dm) {
+ mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1;
+ writel(rwcfg->lfsr_wr_rd_dm_bank_0_data,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ } else {
+ mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1;
+ writel(rwcfg->lfsr_wr_rd_bank_0_data,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(rwcfg->lfsr_wr_rd_bank_0_nop,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ }
+ } else if (rw_wl_nop_cycles == 0) {
+ /*
+ * CNTR 2 - We want to skip the NOP operation and go straight
+ * to the DQS enable instruction. We set the counter to a large
+ * number so that the jump is always taken.
+ */
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
+
+ /* CNTR 3 - Not used */
+ if (test_dm) {
+ mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
+ writel(rwcfg->lfsr_wr_rd_dm_bank_0_dqs,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ } else {
+ mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
+ writel(rwcfg->lfsr_wr_rd_bank_0_dqs,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ }
+ } else {
+ /*
+ * CNTR 2 - In this case we want to execute the next instruction
+ * and NOT take the jump. So we set the counter to 0. The jump
+ * address doesn't count.
+ */
+ writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
+ writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+
+ /*
+ * CNTR 3 - Set the nop counter to the number of cycles we
+ * need to loop for, minus 1.
+ */
+ writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
+ if (test_dm) {
+ mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
+ writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ } else {
+ mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
+ writel(rwcfg->lfsr_wr_rd_bank_0_nop,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ }
+ }
+
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
+
+ if (quick_write_mode)
+ writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
+ else
+ writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
+
+ writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+
/*
- * USER need to wait tMOD (12CK or 15ns) time before issuing
- * other commands, but we will have plenty of NIOS cycles before
- * actual handoff so its okay.
+ * CNTR 1 - This is used to ensure enough time elapses
+ * for read data to come back.
*/
+ writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
+
+ if (test_dm) {
+ writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ } else {
+ writel(rwcfg->lfsr_wr_rd_bank_0_wait,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ }
+
+ writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET) +
+ (group << 2));
+}
+
+/**
+ * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass
+ * @rank_bgn: Rank number
+ * @write_group: Write Group
+ * @use_dm: Use DM
+ * @all_correct: All bits must be correct in the mask
+ * @bit_chk: Resulting bit mask after the test
+ * @all_ranks: Test all ranks
+ *
+ * Test writes, can check for a single bit pass or multiple bit pass.
+ */
+static int
+rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
+ const u32 use_dm, const u32 all_correct,
+ u32 *bit_chk, const u32 all_ranks)
+{
+ const u32 rank_end = all_ranks ?
+ rwcfg->mem_number_of_ranks :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs /
+ rwcfg->mem_virtual_groups_per_write_dqs;
+ const u32 correct_mask_vg = param->write_correct_mask_vg;
+
+ u32 tmp_bit_chk, base_rw_mgr;
+ int vg, r;
+
+ *bit_chk = param->write_correct_mask;
+
+ for (r = rank_bgn; r < rank_end; r++) {
+ /* Set rank */
+ set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
+
+ tmp_bit_chk = 0;
+ for (vg = rwcfg->mem_virtual_groups_per_write_dqs - 1;
+ vg >= 0; vg--) {
+ /* Reset the FIFOs to get pointers to known state. */
+ writel(0, &phy_mgr_cmd->fifo_reset);
+
+ rw_mgr_mem_calibrate_write_test_issue(
+ write_group *
+ rwcfg->mem_virtual_groups_per_write_dqs + vg,
+ use_dm);
+
+ base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
+ tmp_bit_chk <<= shift_ratio;
+ tmp_bit_chk |= (correct_mask_vg & ~(base_rw_mgr));
+ }
+
+ *bit_chk &= tmp_bit_chk;
+ }
+
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ if (all_correct) {
+ debug_cond(DLEVEL == 2,
+ "write_test(%u,%u,ALL) : %u == %u => %i\n",
+ write_group, use_dm, *bit_chk,
+ param->write_correct_mask,
+ *bit_chk == param->write_correct_mask);
+ return *bit_chk == param->write_correct_mask;
+ } else {
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ debug_cond(DLEVEL == 2,
+ "write_test(%u,%u,ONE) : %u != %i => %i\n",
+ write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
+ return *bit_chk != 0x00;
+ }
}
/**
const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
const u32 addr_offset =
- (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
+ (group * rwcfg->mem_virtual_groups_per_read_dqs) << 2;
const u32 rank_end = all_ranks ?
- RW_MGR_MEM_NUMBER_OF_RANKS :
+ rwcfg->mem_number_of_ranks :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ const u32 shift_ratio = rwcfg->mem_dq_per_read_dqs /
+ rwcfg->mem_virtual_groups_per_read_dqs;
const u32 correct_mask_vg = param->read_correct_mask_vg;
u32 tmp_bit_chk, base_rw_mgr, bit_chk;
bit_chk = param->read_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
- /* Request to skip the rank */
- if (param->skip_ranks[r])
- continue;
-
/* Set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts of read commands */
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(RW_MGR_GUARANTEED_READ,
+ writel(rwcfg->guaranteed_read,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_GUARANTEED_READ_CONT,
+ writel(rwcfg->guaranteed_read_cont,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
tmp_bit_chk = 0;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
+ for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1;
vg >= 0; vg--) {
/* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RESET_READ_DATAPATH_OFFSET);
- writel(RW_MGR_GUARANTEED_READ,
+ writel(rwcfg->guaranteed_read,
addr + addr_offset + (vg << 2));
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
bit_chk &= tmp_bit_chk;
}
- writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
+ writel(rwcfg->clear_dqs_enable, addr + (group << 2));
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
const int all_ranks)
{
const u32 rank_end = all_ranks ?
- RW_MGR_MEM_NUMBER_OF_RANKS :
+ rwcfg->mem_number_of_ranks :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
u32 r;
debug("%s:%d\n", __func__, __LINE__);
for (r = rank_bgn; r < rank_end; r++) {
- if (param->skip_ranks[r])
- /* request to skip the rank */
- continue;
-
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts */
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
+ writel(rwcfg->guaranteed_write_wait0,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
+ writel(rwcfg->guaranteed_write_wait1,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
+ writel(rwcfg->guaranteed_write_wait2,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
- writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
+ writel(rwcfg->guaranteed_write_wait3,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
- writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
u32 *bit_chk,
const u32 all_groups, const u32 all_ranks)
{
- const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
+ const u32 rank_end = all_ranks ? rwcfg->mem_number_of_ranks :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
const u32 quick_read_mode =
((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
*bit_chk = param->read_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
- if (param->skip_ranks[r])
- /* request to skip the rank */
- continue;
-
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_READ_B2B_WAIT1,
+ writel(rwcfg->read_b2b_wait1,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
- writel(RW_MGR_READ_B2B_WAIT2,
+ writel(rwcfg->read_b2b_wait2,
&sdr_rw_load_jump_mgr_regs->load_jump_add2);
if (quick_read_mode)
else
writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(RW_MGR_READ_B2B,
+ writel(rwcfg->read_b2b,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
if (all_groups)
- writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
+ writel(rwcfg->mem_if_read_dqs_width *
+ rwcfg->mem_virtual_groups_per_read_dqs - 1,
&sdr_rw_load_mgr_regs->load_cntr3);
else
writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
- writel(RW_MGR_READ_B2B,
+ writel(rwcfg->read_b2b,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
tmp_bit_chk = 0;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
+ for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0;
vg--) {
/* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
}
- writel(RW_MGR_READ_B2B, addr +
- ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
+ writel(rwcfg->read_b2b, addr +
+ ((group * rwcfg->mem_virtual_groups_per_read_dqs +
vg) << 2));
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
- tmp_bit_chk <<= RW_MGR_MEM_DQ_PER_READ_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs /
+ rwcfg->mem_virtual_groups_per_read_dqs;
tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
}
}
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
+ writel(rwcfg->clear_dqs_enable, addr + (group << 2));
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
{
u32 i;
- for (i = 0; i < VFIFO_SIZE - 1; i++)
+ for (i = 0; i < READ_VALID_FIFO_SIZE - 1; i++)
rw_mgr_incr_vfifo(grp);
}
{
u32 v, ret, fail_cnt = 0;
- for (v = 0; v < VFIFO_SIZE; v++) {
+ for (v = 0; v < READ_VALID_FIFO_SIZE; v++) {
debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
__func__, __LINE__, v);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
static int sdr_find_phase_delay(int working, int delay, const u32 grp,
u32 *work, const u32 work_inc, u32 *pd)
{
- const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
+ const u32 max = delay ? iocfg->dqs_en_delay_max : iocfg->dqs_en_phase_max;
u32 ret;
for (; *pd <= max; (*pd)++) {
static int sdr_find_phase(int working, const u32 grp, u32 *work,
u32 *i, u32 *p)
{
- const u32 end = VFIFO_SIZE + (working ? 0 : 1);
+ const u32 end = READ_VALID_FIFO_SIZE + (working ? 0 : 1);
int ret;
for (; *i < end; (*i)++) {
*p = 0;
ret = sdr_find_phase_delay(working, 0, grp, work,
- IO_DELAY_PER_OPA_TAP, p);
+ iocfg->delay_per_opa_tap, p);
if (!ret)
return 0;
- if (*p > IO_DQS_EN_PHASE_MAX) {
+ if (*p > iocfg->dqs_en_phase_max) {
/* Fiddle with FIFO. */
rw_mgr_incr_vfifo(grp);
if (!working)
static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
u32 *p, u32 *i)
{
- const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ const u32 dtaps_per_ptap = iocfg->delay_per_opa_tap /
+ iocfg->delay_per_dqs_en_dchain_tap;
int ret;
*work_bgn = 0;
ret = sdr_find_phase(1, grp, work_bgn, i, p);
if (!ret)
return 0;
- *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ *work_bgn += iocfg->delay_per_dqs_en_dchain_tap;
}
/* Cannot find working solution */
/* Special case code for backing up a phase */
if (*p == 0) {
- *p = IO_DQS_EN_PHASE_MAX;
+ *p = iocfg->dqs_en_phase_max;
rw_mgr_decr_vfifo(grp);
} else {
(*p)--;
}
- tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
+ tmp_delay = *work_bgn - iocfg->delay_per_opa_tap;
scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
- for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
+ for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; d++) {
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
break;
}
- tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ tmp_delay += iocfg->delay_per_dqs_en_dchain_tap;
}
/* Restore VFIFO to old state before we decremented it (if needed). */
(*p)++;
- if (*p > IO_DQS_EN_PHASE_MAX) {
+ if (*p > iocfg->dqs_en_phase_max) {
*p = 0;
rw_mgr_incr_vfifo(grp);
}
int ret;
(*p)++;
- *work_end += IO_DELAY_PER_OPA_TAP;
- if (*p > IO_DQS_EN_PHASE_MAX) {
+ *work_end += iocfg->delay_per_opa_tap;
+ if (*p > iocfg->dqs_en_phase_max) {
/* Fiddle with FIFO. */
*p = 0;
rw_mgr_incr_vfifo(grp);
debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
work_bgn, work_end, work_mid);
/* Get the middle delay to be less than a VFIFO delay */
- tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
+ tmp_delay = (iocfg->dqs_en_phase_max + 1) * iocfg->delay_per_opa_tap;
debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
work_mid %= tmp_delay;
debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
- tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
- if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
- tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
- p = tmp_delay / IO_DELAY_PER_OPA_TAP;
+ tmp_delay = rounddown(work_mid, iocfg->delay_per_opa_tap);
+ if (tmp_delay > iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap)
+ tmp_delay = iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap;
+ p = tmp_delay / iocfg->delay_per_opa_tap;
debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
- d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
- if (d > IO_DQS_EN_DELAY_MAX)
- d = IO_DQS_EN_DELAY_MAX;
- tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ d = DIV_ROUND_UP(work_mid - tmp_delay, iocfg->delay_per_dqs_en_dchain_tap);
+ if (d > iocfg->dqs_en_delay_max)
+ d = iocfg->dqs_en_delay_max;
+ tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap;
debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
* push vfifo until we can successfully calibrate. We can do this
* because the largest possible margin in 1 VFIFO cycle.
*/
- for (i = 0; i < VFIFO_SIZE; i++) {
+ for (i = 0; i < READ_VALID_FIFO_SIZE; i++) {
debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
/* Step 0: Determine number of delay taps for each phase tap. */
- dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ dtaps_per_ptap = iocfg->delay_per_opa_tap / iocfg->delay_per_dqs_en_dchain_tap;
/* Step 1: First push vfifo until we get a failing read. */
find_vfifo_failing_read(grp);
/* Special case code for backing up a phase */
if (p == 0) {
- p = IO_DQS_EN_PHASE_MAX;
+ p = iocfg->dqs_en_phase_max;
rw_mgr_decr_vfifo(grp);
} else {
p = p - 1;
}
- work_end -= IO_DELAY_PER_OPA_TAP;
+ work_end -= iocfg->delay_per_opa_tap;
scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
d = 0;
/* The dtap increment to find the failing edge is done here. */
sdr_find_phase_delay(0, 1, grp, &work_end,
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
+ iocfg->delay_per_dqs_en_dchain_tap, &d);
/* Go back to working dtap */
if (d != 0)
- work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ work_end -= iocfg->delay_per_dqs_en_dchain_tap;
debug_cond(DLEVEL == 2,
"%s:%d p/d: ptap=%u dtap=%u end=%u\n",
/* Special case code for backing up a phase */
if (p == 0) {
- p = IO_DQS_EN_PHASE_MAX;
+ p = iocfg->dqs_en_phase_max;
rw_mgr_decr_vfifo(grp);
debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
__func__, __LINE__, p);
/*
* The dynamically calculated dtaps_per_ptap is only valid if we
* found a passing/failing read. If we didn't, it means d hit the max
- * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
+ * (iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its
* statically calculated value.
*/
if (found_passing_read && found_failing_read)
u32 *bit_chk, u32 *sticky_bit_chk,
const u32 use_read_test)
{
- const u32 ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const u32 ratio = rwcfg->mem_if_read_dqs_width /
+ rwcfg->mem_if_write_dqs_width;
const u32 correct_mask = write ? param->write_correct_mask :
param->read_correct_mask;
- const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
- RW_MGR_MEM_DQ_PER_READ_DQS;
+ const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ rwcfg->mem_dq_per_read_dqs;
u32 ret;
/*
* Stop searching when the read test doesn't pass AND when
* @write_group: Write Group
* @read_group: Read Group
* @test_bgn: Rank number to begin the test
- * @bit_chk: Resulting bit mask after the test
* @sticky_bit_chk: Resulting sticky bit mask after the test
* @left_edge: Left edge of the DQ/DQS phase
* @right_edge: Right edge of the DQ/DQS phase
*/
static void search_left_edge(const int write, const int rank_bgn,
const u32 write_group, const u32 read_group, const u32 test_bgn,
- u32 *bit_chk, u32 *sticky_bit_chk,
+ u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
- const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
- const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
- const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
- RW_MGR_MEM_DQ_PER_READ_DQS;
- u32 stop;
+ const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
+ const u32 dqs_max = write ? iocfg->io_out1_delay_max : iocfg->dqs_in_delay_max;
+ const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ rwcfg->mem_dq_per_read_dqs;
+ u32 stop, bit_chk;
int i, d;
for (d = 0; d <= dqs_max; d++) {
writel(0, &sdr_scc_mgr->update);
stop = search_stop_check(write, d, rank_bgn, write_group,
- read_group, bit_chk, sticky_bit_chk,
+ read_group, &bit_chk, sticky_bit_chk,
use_read_test);
if (stop == 1)
break;
/* stop != 1 */
for (i = 0; i < per_dqs; i++) {
- if (*bit_chk & 1) {
+ if (bit_chk & 1) {
/*
* Remember a passing test as
* the left_edge.
if (left_edge[i] == delay_max + 1)
right_edge[i] = -(d + 1);
}
- *bit_chk = *bit_chk >> 1;
+ bit_chk >>= 1;
}
}
* @read_group: Read Group
* @start_dqs: DQS start phase
* @start_dqs_en: DQS enable start phase
- * @bit_chk: Resulting bit mask after the test
* @sticky_bit_chk: Resulting sticky bit mask after the test
* @left_edge: Left edge of the DQ/DQS phase
* @right_edge: Right edge of the DQ/DQS phase
static int search_right_edge(const int write, const int rank_bgn,
const u32 write_group, const u32 read_group,
const int start_dqs, const int start_dqs_en,
- u32 *bit_chk, u32 *sticky_bit_chk,
+ u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
- const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
- const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
- const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
- RW_MGR_MEM_DQ_PER_READ_DQS;
- u32 stop;
+ const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
+ const u32 dqs_max = write ? iocfg->io_out1_delay_max : iocfg->dqs_in_delay_max;
+ const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ rwcfg->mem_dq_per_read_dqs;
+ u32 stop, bit_chk;
int i, d;
for (d = 0; d <= dqs_max - start_dqs; d++) {
d + start_dqs);
} else { /* READ-ONLY */
scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
+ if (iocfg->shift_dqs_en_when_shift_dqs) {
uint32_t delay = d + start_dqs_en;
- if (delay > IO_DQS_EN_DELAY_MAX)
- delay = IO_DQS_EN_DELAY_MAX;
+ if (delay > iocfg->dqs_en_delay_max)
+ delay = iocfg->dqs_en_delay_max;
scc_mgr_set_dqs_en_delay(read_group, delay);
}
scc_mgr_load_dqs(read_group);
writel(0, &sdr_scc_mgr->update);
stop = search_stop_check(write, d, rank_bgn, write_group,
- read_group, bit_chk, sticky_bit_chk,
+ read_group, &bit_chk, sticky_bit_chk,
use_read_test);
if (stop == 1) {
if (write && (d == 0)) { /* WRITE-ONLY */
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
/*
* d = 0 failed, but it passed when
* testing the left edge, so it must be
/* stop != 1 */
for (i = 0; i < per_dqs; i++) {
- if (*bit_chk & 1) {
+ if (bit_chk & 1) {
/*
* Remember a passing test as
* the right_edge.
__func__, __LINE__, d);
debug_cond(DLEVEL == 2,
"bit_chk_test=%i left_edge[%u]: %d ",
- *bit_chk & 1, i, left_edge[i]);
+ bit_chk & 1, i, left_edge[i]);
debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
right_edge[i]);
- *bit_chk = *bit_chk >> 1;
+ bit_chk >>= 1;
}
}
static int get_window_mid_index(const int write, int *left_edge,
int *right_edge, int *mid_min)
{
- const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
- RW_MGR_MEM_DQ_PER_READ_DQS;
+ const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ rwcfg->mem_dq_per_read_dqs;
int i, mid, min_index;
/* Find middle of window for each DQ bit */
return min_index;
}
-/* per-bit deskew DQ and center */
-static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
- uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
- uint32_t use_read_test, uint32_t update_fom)
+/**
+ * center_dq_windows() - Center the DQ/DQS windows
+ * @write: Perform read (Stage 2) or write (Stage 3) calibration
+ * @left_edge: Left edge of the DQ/DQS phase
+ * @right_edge: Right edge of the DQ/DQS phase
+ * @mid_min: Adjusted DQ/DQS phase middle setting
+ * @orig_mid_min: Original DQ/DQS phase middle setting
+ * @min_index: DQ/DQS phase middle setting index
+ * @test_bgn: Rank number to begin the test
+ * @dq_margin: Amount of shift for the DQ
+ * @dqs_margin: Amount of shift for the DQS
+ *
+ * Align the DQ/DQS windows in each group.
+ */
+static void center_dq_windows(const int write, int *left_edge, int *right_edge,
+ const int mid_min, const int orig_mid_min,
+ const int min_index, const int test_bgn,
+ int *dq_margin, int *dqs_margin)
{
- uint32_t p, min_index;
- int i;
+ const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
+ const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ rwcfg->mem_dq_per_read_dqs;
+ const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
+ SCC_MGR_IO_IN_DELAY_OFFSET;
+ const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
+
+ u32 temp_dq_io_delay1, temp_dq_io_delay2;
+ int shift_dq, i, p;
+
+ /* Initialize data for export structures */
+ *dqs_margin = delay_max + 1;
+ *dq_margin = delay_max + 1;
+
+ /* add delay to bring centre of all DQ windows to the same "level" */
+ for (i = 0, p = test_bgn; i < per_dqs; i++, p++) {
+ /* Use values before divide by 2 to reduce round off error */
+ shift_dq = (left_edge[i] - right_edge[i] -
+ (left_edge[min_index] - right_edge[min_index]))/2 +
+ (orig_mid_min - mid_min);
+
+ debug_cond(DLEVEL == 2,
+ "vfifo_center: before: shift_dq[%u]=%d\n",
+ i, shift_dq);
+
+ temp_dq_io_delay1 = readl(addr + (p << 2));
+ temp_dq_io_delay2 = readl(addr + (i << 2));
+
+ if (shift_dq + temp_dq_io_delay1 > delay_max)
+ shift_dq = delay_max - temp_dq_io_delay2;
+ else if (shift_dq + temp_dq_io_delay1 < 0)
+ shift_dq = -temp_dq_io_delay1;
+
+ debug_cond(DLEVEL == 2,
+ "vfifo_center: after: shift_dq[%u]=%d\n",
+ i, shift_dq);
+
+ if (write)
+ scc_mgr_set_dq_out1_delay(i, temp_dq_io_delay1 + shift_dq);
+ else
+ scc_mgr_set_dq_in_delay(p, temp_dq_io_delay1 + shift_dq);
+
+ scc_mgr_load_dq(p);
+
+ debug_cond(DLEVEL == 2,
+ "vfifo_center: margin[%u]=[%d,%d]\n", i,
+ left_edge[i] - shift_dq + (-mid_min),
+ right_edge[i] + shift_dq - (-mid_min));
+
+ /* To determine values for export structures */
+ if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin)
+ *dq_margin = left_edge[i] - shift_dq + (-mid_min);
+
+ if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
+ *dqs_margin = right_edge[i] + shift_dq - (-mid_min);
+ }
+
+}
+
+/**
+ * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering
+ * @rank_bgn: Rank number
+ * @rw_group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ * @use_read_test: Perform a read test
+ * @update_fom: Update FOM
+ *
+ * Per-bit deskew DQ and centering.
+ */
+static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
+ const u32 rw_group, const u32 test_bgn,
+ const int use_read_test, const int update_fom)
+{
+ const u32 addr =
+ SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
+ (rw_group << 2);
/*
* Store these as signed since there are comparisons with
* signed numbers.
*/
- uint32_t bit_chk;
uint32_t sticky_bit_chk;
- int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
- int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
- int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
- int32_t mid;
+ int32_t left_edge[rwcfg->mem_dq_per_read_dqs];
+ int32_t right_edge[rwcfg->mem_dq_per_read_dqs];
int32_t orig_mid_min, mid_min;
- int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
- final_dqs_en;
+ int32_t new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en;
int32_t dq_margin, dqs_margin;
- uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
- uint32_t addr;
+ int i, min_index;
int ret;
- debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
+ debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
- start_dqs = readl(addr + (read_group << 2));
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
- start_dqs_en = readl(addr + ((read_group << 2)
- - IO_DQS_EN_DELAY_OFFSET));
+ start_dqs = readl(addr);
+ if (iocfg->shift_dqs_en_when_shift_dqs)
+ start_dqs_en = readl(addr - iocfg->dqs_en_delay_offset);
/* set the left and right edge of each bit to an illegal value */
- /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
+ /* use (iocfg->io_in_delay_max + 1) as an illegal value */
sticky_bit_chk = 0;
- for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
- left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
- right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
+ for (i = 0; i < rwcfg->mem_dq_per_read_dqs; i++) {
+ left_edge[i] = iocfg->io_in_delay_max + 1;
+ right_edge[i] = iocfg->io_in_delay_max + 1;
}
/* Search for the left edge of the window for each bit */
- search_left_edge(0, rank_bgn, write_group, read_group, test_bgn,
- &bit_chk, &sticky_bit_chk,
+ search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn,
+ &sticky_bit_chk,
left_edge, right_edge, use_read_test);
/* Search for the right edge of the window for each bit */
- ret = search_right_edge(0, rank_bgn, write_group, read_group,
+ ret = search_right_edge(0, rank_bgn, rw_group, rw_group,
start_dqs, start_dqs_en,
- &bit_chk, &sticky_bit_chk,
+ &sticky_bit_chk,
left_edge, right_edge, use_read_test);
if (ret) {
/*
* in rw_mgr_mem_calibrate_vfifo to retry different
* dqs/ck relationships.
*/
- scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
- scc_mgr_set_dqs_en_delay(read_group, start_dqs_en);
+ scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
+ if (iocfg->shift_dqs_en_when_shift_dqs)
+ scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
- scc_mgr_load_dqs(read_group);
+ scc_mgr_load_dqs(rw_group);
writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL == 1,
"%s:%d vfifo_center: failed to find edge [%u]: %d %d",
__func__, __LINE__, i, left_edge[i], right_edge[i]);
if (use_read_test) {
- set_failing_group_stage(read_group *
- RW_MGR_MEM_DQ_PER_READ_DQS + i,
+ set_failing_group_stage(rw_group *
+ rwcfg->mem_dq_per_read_dqs + i,
CAL_STAGE_VFIFO,
CAL_SUBSTAGE_VFIFO_CENTER);
} else {
- set_failing_group_stage(read_group *
- RW_MGR_MEM_DQ_PER_READ_DQS + i,
+ set_failing_group_stage(rw_group *
+ rwcfg->mem_dq_per_read_dqs + i,
CAL_STAGE_VFIFO_AFTER_WRITES,
CAL_SUBSTAGE_VFIFO_CENTER);
}
- return 0;
+ return -EIO;
}
min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min);
/* Determine the amount we can change DQS (which is -mid_min) */
orig_mid_min = mid_min;
new_dqs = start_dqs - mid_min;
- if (new_dqs > IO_DQS_IN_DELAY_MAX)
- new_dqs = IO_DQS_IN_DELAY_MAX;
+ if (new_dqs > iocfg->dqs_in_delay_max)
+ new_dqs = iocfg->dqs_in_delay_max;
else if (new_dqs < 0)
new_dqs = 0;
debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
mid_min, new_dqs);
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
- if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
- mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
+ if (iocfg->shift_dqs_en_when_shift_dqs) {
+ if (start_dqs_en - mid_min > iocfg->dqs_en_delay_max)
+ mid_min += start_dqs_en - mid_min - iocfg->dqs_en_delay_max;
else if (start_dqs_en - mid_min < 0)
mid_min += start_dqs_en - mid_min;
}
debug_cond(DLEVEL == 1,
"vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
start_dqs,
- IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
+ iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1,
new_dqs, mid_min);
- /* Initialize data for export structures */
- dqs_margin = IO_IO_IN_DELAY_MAX + 1;
- dq_margin = IO_IO_IN_DELAY_MAX + 1;
-
- /* add delay to bring centre of all DQ windows to the same "level" */
- for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
- /* Use values before divide by 2 to reduce round off error */
- shift_dq = (left_edge[i] - right_edge[i] -
- (left_edge[min_index] - right_edge[min_index]))/2 +
- (orig_mid_min - mid_min);
-
- debug_cond(DLEVEL == 2,
- "vfifo_center: before: shift_dq[%u]=%d\n",
- i, shift_dq);
+ /* Add delay to bring centre of all DQ windows to the same "level". */
+ center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min,
+ min_index, test_bgn, &dq_margin, &dqs_margin);
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
- temp_dq_in_delay1 = readl(addr + (p << 2));
- temp_dq_in_delay2 = readl(addr + (i << 2));
+ /* Move DQS-en */
+ if (iocfg->shift_dqs_en_when_shift_dqs) {
+ final_dqs_en = start_dqs_en - mid_min;
+ scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
+ scc_mgr_load_dqs(rw_group);
+ }
- if (shift_dq + temp_dq_in_delay1 > IO_IO_IN_DELAY_MAX)
- shift_dq = IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
- else if (shift_dq + temp_dq_in_delay1 < 0)
- shift_dq = -temp_dq_in_delay1;
-
- debug_cond(DLEVEL == 2,
- "vfifo_center: after: shift_dq[%u]=%d\n",
- i, shift_dq);
- final_dq[i] = temp_dq_in_delay1 + shift_dq;
- scc_mgr_set_dq_in_delay(p, final_dq[i]);
- scc_mgr_load_dq(p);
-
- debug_cond(DLEVEL == 2,
- "vfifo_center: margin[%u]=[%d,%d]\n", i,
- left_edge[i] - shift_dq + (-mid_min),
- right_edge[i] + shift_dq - (-mid_min));
-
- /* To determine values for export structures */
- if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
- dq_margin = left_edge[i] - shift_dq + (-mid_min);
-
- if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
- dqs_margin = right_edge[i] + shift_dq - (-mid_min);
- }
-
- final_dqs = new_dqs;
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
- final_dqs_en = start_dqs_en - mid_min;
-
- /* Move DQS-en */
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
- scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
- scc_mgr_load_dqs(read_group);
- }
-
- /* Move DQS */
- scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
- scc_mgr_load_dqs(read_group);
- debug_cond(DLEVEL == 2,
- "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
- __func__, __LINE__, dq_margin, dqs_margin);
+ /* Move DQS */
+ scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
+ scc_mgr_load_dqs(rw_group);
+ debug_cond(DLEVEL == 2,
+ "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
+ __func__, __LINE__, dq_margin, dqs_margin);
/*
* Do not remove this line as it makes sure all of our decisions
*/
writel(0, &sdr_scc_mgr->update);
- return (dq_margin >= 0) && (dqs_margin >= 0);
+ if ((dq_margin < 0) || (dqs_margin < 0))
+ return -EINVAL;
+
+ return 0;
}
/**
*/
/* We start at zero, so have one less dq to devide among */
- const u32 delay_step = IO_IO_IN_DELAY_MAX /
- (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
+ const u32 delay_step = iocfg->io_in_delay_max /
+ (rwcfg->mem_dq_per_read_dqs - 1);
int ret;
u32 i, p, d, r;
debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
/* Try different dq_in_delays since the DQ path is shorter than DQS. */
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
for (i = 0, p = test_bgn, d = 0;
- i < RW_MGR_MEM_DQ_PER_READ_DQS;
+ i < rwcfg->mem_dq_per_read_dqs;
i++, p++, d += delay_step) {
debug_cond(DLEVEL == 1,
"%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
"%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
__func__, __LINE__, rw_group, !ret);
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
writel(0, &sdr_scc_mgr->update);
*/
grp_calibrated = 1;
for (rank_bgn = 0, sr = 0;
- rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn < rwcfg->mem_number_of_ranks;
rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
- /* Check if this set of ranks should be skipped entirely. */
- if (param->skip_shadow_regs[sr])
- continue;
-
ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
- rw_group, test_bgn,
+ test_bgn,
use_read_test,
update_fom);
- if (ret)
+ if (!ret)
continue;
grp_calibrated = 0;
failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
/* USER Determine number of delay taps for each phase tap. */
- dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
+ dtaps_per_ptap = DIV_ROUND_UP(iocfg->delay_per_opa_tap,
+ iocfg->delay_per_dqs_en_dchain_tap) - 1;
for (d = 0; d <= dtaps_per_ptap; d += 2) {
/*
rw_group, d);
}
- for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
+ for (p = 0; p <= iocfg->dqdqs_out_phase_max; p++) {
/* 1) Guaranteed Write */
ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
if (ret)
return 1;
}
-/* VFIFO Calibration -- Read Deskew Calibration after write deskew */
-static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
- uint32_t test_bgn)
+/**
+ * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering.
+ * @rw_group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ *
+ * Stage 3: DQ/DQS Centering.
+ *
+ * This function implements UniPHY calibration Stage 3, as explained in
+ * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
+ */
+static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group,
+ const u32 test_bgn)
{
- uint32_t rank_bgn, sr;
- uint32_t grp_calibrated;
- uint32_t write_group;
+ int ret;
- debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
-
- /* update info for sims */
+ debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn);
+ /* Update info for sims. */
+ reg_file_set_group(rw_group);
reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
- write_group = read_group;
-
- /* update info for sims */
- reg_file_set_group(read_group);
-
- grp_calibrated = 1;
- /* Read per-bit deskew can be done on a per shadow register basis */
- for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
- /* Determine if this set of ranks should be skipped entirely */
- if (!param->skip_shadow_regs[sr]) {
- /* This is the last calibration round, update FOM here */
- if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
- write_group,
- read_group,
- test_bgn, 0,
- 1)) {
- grp_calibrated = 0;
- }
- }
- }
-
-
- if (grp_calibrated == 0) {
- set_failing_group_stage(write_group,
+ ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1);
+ if (ret)
+ set_failing_group_stage(rw_group,
CAL_STAGE_VFIFO_AFTER_WRITES,
CAL_SUBSTAGE_VFIFO_CENTER);
- return 0;
- }
-
- return 1;
+ return ret;
}
-/* Calibrate LFIFO to find smallest read latency */
+/**
+ * rw_mgr_mem_calibrate_lfifo() - Minimize latency
+ *
+ * Stage 4: Minimize latency.
+ *
+ * This function implements UniPHY calibration Stage 4, as explained in
+ * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
+ * Calibrate LFIFO to find smallest read latency.
+ */
static uint32_t rw_mgr_mem_calibrate_lfifo(void)
{
- uint32_t found_one;
+ int found_one = 0;
debug("%s:%d\n", __func__, __LINE__);
- /* update info for sims */
+ /* Update info for sims. */
reg_file_set_stage(CAL_STAGE_LFIFO);
reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
/* Load up the patterns used by read calibration for all ranks */
rw_mgr_mem_calibrate_read_load_patterns(0, 1);
- found_one = 0;
do {
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
__func__, __LINE__, gbl->curr_read_lat);
- if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
- NUM_READ_TESTS,
- PASS_ALL_BITS,
- 1)) {
+ if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS,
+ PASS_ALL_BITS, 1))
break;
- }
found_one = 1;
- /* reduce read latency and see if things are working */
- /* correctly */
+ /*
+ * Reduce read latency and see if things are
+ * working correctly.
+ */
gbl->curr_read_lat--;
} while (gbl->curr_read_lat > 0);
- /* reset the fifos to get pointers to known state */
-
+ /* Reset the fifos to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
if (found_one) {
- /* add a fudge factor to the read latency that was determined */
+ /* Add a fudge factor to the read latency that was determined */
gbl->curr_read_lat += 2;
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
- debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
- read_lat=%u\n", __func__, __LINE__,
- gbl->curr_read_lat);
- return 1;
+ debug_cond(DLEVEL == 2,
+ "%s:%d lfifo: success: using read_lat=%u\n",
+ __func__, __LINE__, gbl->curr_read_lat);
} else {
set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
CAL_SUBSTAGE_READ_LATENCY);
- debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
- read_lat=%u\n", __func__, __LINE__,
- gbl->curr_read_lat);
- return 0;
+ debug_cond(DLEVEL == 2,
+ "%s:%d lfifo: failed at initial read_lat=%u\n",
+ __func__, __LINE__, gbl->curr_read_lat);
}
+
+ return found_one;
}
-/*
- * issue write test command.
- * two variants are provided. one that just tests a write pattern and
- * another that tests datamask functionality.
+/**
+ * search_window() - Search for the/part of the window with DM/DQS shift
+ * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
+ * @rank_bgn: Rank number
+ * @write_group: Write Group
+ * @bgn_curr: Current window begin
+ * @end_curr: Current window end
+ * @bgn_best: Current best window begin
+ * @end_best: Current best window end
+ * @win_best: Size of the best window
+ * @new_dqs: New DQS value (only applicable if search_dm = 0).
+ *
+ * Search for the/part of the window with DM/DQS shift.
*/
-static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
- uint32_t test_dm)
+static void search_window(const int search_dm,
+ const u32 rank_bgn, const u32 write_group,
+ int *bgn_curr, int *end_curr, int *bgn_best,
+ int *end_best, int *win_best, int new_dqs)
{
- uint32_t mcc_instruction;
- uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
- ENABLE_SUPER_QUICK_CALIBRATION);
- uint32_t rw_wl_nop_cycles;
- uint32_t addr;
-
- /*
- * Set counter and jump addresses for the right
- * number of NOP cycles.
- * The number of supported NOP cycles can range from -1 to infinity
- * Three different cases are handled:
- *
- * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
- * mechanism will be used to insert the right number of NOPs
- *
- * 2. For a number of NOP cycles equals to 0, the micro-instruction
- * issuing the write command will jump straight to the
- * micro-instruction that turns on DQS (for DDRx), or outputs write
- * data (for RLD), skipping
- * the NOP micro-instruction all together
- *
- * 3. A number of NOP cycles equal to -1 indicates that DQS must be
- * turned on in the same micro-instruction that issues the write
- * command. Then we need
- * to directly jump to the micro-instruction that sends out the data
- *
- * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
- * (2 and 3). One jump-counter (0) is used to perform multiple
- * write-read operations.
- * one counter left to issue this command in "multiple-group" mode
- */
-
- rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
-
- if (rw_wl_nop_cycles == -1) {
- /*
- * CNTR 2 - We want to execute the special write operation that
- * turns on DQS right away and then skip directly to the
- * instruction that sends out the data. We set the counter to a
- * large number so that the jump is always taken.
- */
- writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
-
- /* CNTR 3 - Not used */
- if (test_dm) {
- mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
- } else {
- mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
- }
- } else if (rw_wl_nop_cycles == 0) {
- /*
- * CNTR 2 - We want to skip the NOP operation and go straight
- * to the DQS enable instruction. We set the counter to a large
- * number so that the jump is always taken.
- */
- writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
-
- /* CNTR 3 - Not used */
- if (test_dm) {
- mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- } else {
- mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- }
- } else {
- /*
- * CNTR 2 - In this case we want to execute the next instruction
- * and NOT take the jump. So we set the counter to 0. The jump
- * address doesn't count.
- */
- writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
- writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
-
- /*
- * CNTR 3 - Set the nop counter to the number of cycles we
- * need to loop for, minus 1.
- */
- writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
- if (test_dm) {
- mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ u32 bit_chk;
+ const int max = iocfg->io_out1_delay_max - new_dqs;
+ int d, di;
+
+ /* Search for the/part of the window with DM/DQS shift. */
+ for (di = max; di >= 0; di -= DELTA_D) {
+ if (search_dm) {
+ d = di;
+ scc_mgr_apply_group_dm_out1_delay(d);
} else {
- mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ /* For DQS, we go from 0...max */
+ d = max - di;
+ /*
+ * Note: This only shifts DQS, so are we limiting ourselve to
+ * width of DQ unnecessarily.
+ */
+ scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
+ d + new_dqs);
}
- }
-
- writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RESET_READ_DATAPATH_OFFSET);
-
- if (quick_write_mode)
- writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
- else
- writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
-
- writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
-
- /*
- * CNTR 1 - This is used to ensure enough time elapses
- * for read data to come back.
- */
- writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
- if (test_dm) {
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- } else {
- writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- }
-
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(mcc_instruction, addr + (group << 2));
-}
-
-/* Test writes, can check for a single bit pass or multiple bit pass */
-static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
- uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
- uint32_t *bit_chk, uint32_t all_ranks)
-{
- uint32_t r;
- uint32_t correct_mask_vg;
- uint32_t tmp_bit_chk;
- uint32_t vg;
- uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
- (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- uint32_t addr_rw_mgr;
- uint32_t base_rw_mgr;
-
- *bit_chk = param->write_correct_mask;
- correct_mask_vg = param->write_correct_mask_vg;
+ writel(0, &sdr_scc_mgr->update);
- for (r = rank_bgn; r < rank_end; r++) {
- if (param->skip_ranks[r]) {
- /* request to skip the rank */
- continue;
- }
+ if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
+ PASS_ALL_BITS, &bit_chk,
+ 0)) {
+ /* Set current end of the window. */
+ *end_curr = search_dm ? -d : d;
- /* set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
+ /*
+ * If a starting edge of our window has not been seen
+ * this is our current start of the DM window.
+ */
+ if (*bgn_curr == iocfg->io_out1_delay_max + 1)
+ *bgn_curr = search_dm ? -d : d;
- tmp_bit_chk = 0;
- addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
- /* reset the fifos to get pointers to known state */
- writel(0, &phy_mgr_cmd->fifo_reset);
+ /*
+ * If current window is bigger than best seen.
+ * Set best seen to be current window.
+ */
+ if ((*end_curr - *bgn_curr + 1) > *win_best) {
+ *win_best = *end_curr - *bgn_curr + 1;
+ *bgn_best = *bgn_curr;
+ *end_best = *end_curr;
+ }
+ } else {
+ /* We just saw a failing test. Reset temp edge. */
+ *bgn_curr = iocfg->io_out1_delay_max + 1;
+ *end_curr = iocfg->io_out1_delay_max + 1;
- tmp_bit_chk = tmp_bit_chk <<
- (RW_MGR_MEM_DQ_PER_WRITE_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
- rw_mgr_mem_calibrate_write_test_issue(write_group *
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
- use_dm);
+ /* Early exit is only applicable to DQS. */
+ if (search_dm)
+ continue;
- base_rw_mgr = readl(addr_rw_mgr);
- tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
- if (vg == 0)
+ /*
+ * Early exit optimization: if the remaining delay
+ * chain space is less than already seen largest
+ * window we can exit.
+ */
+ if (*win_best - 1 > iocfg->io_out1_delay_max - new_dqs - d)
break;
}
- *bit_chk &= tmp_bit_chk;
- }
-
- if (all_correct) {
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
- %u => %lu", write_group, use_dm,
- *bit_chk, param->write_correct_mask,
- (long unsigned int)(*bit_chk ==
- param->write_correct_mask));
- return *bit_chk == param->write_correct_mask;
- } else {
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
- write_group, use_dm, *bit_chk);
- debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
- (long unsigned int)(*bit_chk != 0));
- return *bit_chk != 0x00;
}
}
/*
- * center all windows. do per-bit-deskew to possibly increase size of
+ * rw_mgr_mem_calibrate_writes_center() - Center all windows
+ * @rank_bgn: Rank number
+ * @write_group: Write group
+ * @test_bgn: Rank at which the test begins
+ *
+ * Center all windows. Do per-bit-deskew to possibly increase size of
* certain windows.
*/
-static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
- uint32_t write_group, uint32_t test_bgn)
+static int
+rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
+ const u32 test_bgn)
{
- uint32_t i, p, min_index;
- int32_t d;
- /*
- * Store these as signed since there are comparisons with
- * signed numbers.
- */
- uint32_t bit_chk;
- uint32_t sticky_bit_chk;
- int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
- int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
- int32_t mid;
- int32_t mid_min, orig_mid_min;
- int32_t new_dqs, start_dqs, shift_dq;
- int32_t dq_margin, dqs_margin, dm_margin;
- uint32_t temp_dq_out1_delay;
- uint32_t addr;
+ int i;
+ u32 sticky_bit_chk;
+ u32 min_index;
+ int left_edge[rwcfg->mem_dq_per_write_dqs];
+ int right_edge[rwcfg->mem_dq_per_write_dqs];
+ int mid;
+ int mid_min, orig_mid_min;
+ int new_dqs, start_dqs;
+ int dq_margin, dqs_margin, dm_margin;
+ int bgn_curr = iocfg->io_out1_delay_max + 1;
+ int end_curr = iocfg->io_out1_delay_max + 1;
+ int bgn_best = iocfg->io_out1_delay_max + 1;
+ int end_best = iocfg->io_out1_delay_max + 1;
+ int win_best = 0;
int ret;
dm_margin = 0;
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
- start_dqs = readl(addr +
- (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+ start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_IO_OUT1_DELAY_OFFSET) +
+ (rwcfg->mem_dq_per_write_dqs << 2));
- /* per-bit deskew */
+ /* Per-bit deskew. */
/*
- * set the left and right edge of each bit to an illegal value
- * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
+ * Set the left and right edge of each bit to an illegal value.
+ * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
*/
sticky_bit_chk = 0;
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
- left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
- right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
+ left_edge[i] = iocfg->io_out1_delay_max + 1;
+ right_edge[i] = iocfg->io_out1_delay_max + 1;
}
- /* Search for the left edge of the window for each bit */
+ /* Search for the left edge of the window for each bit. */
search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
- &bit_chk, &sticky_bit_chk,
+ &sticky_bit_chk,
left_edge, right_edge, 0);
- /* Search for the right edge of the window for each bit */
+ /* Search for the right edge of the window for each bit. */
ret = search_right_edge(1, rank_bgn, write_group, 0,
start_dqs, 0,
- &bit_chk, &sticky_bit_chk,
+ &sticky_bit_chk,
left_edge, right_edge, 0);
if (ret) {
set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
CAL_SUBSTAGE_WRITES_CENTER);
- return 0;
+ return -EINVAL;
}
min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
- /* Determine the amount we can change DQS (which is -mid_min) */
+ /* Determine the amount we can change DQS (which is -mid_min). */
orig_mid_min = mid_min;
new_dqs = start_dqs;
mid_min = 0;
- debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
- mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
- /* Initialize data for export structures */
- dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
- dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
-
- /* add delay to bring centre of all DQ windows to the same "level" */
- for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
- /* Use values before divide by 2 to reduce round off error */
- shift_dq = (left_edge[i] - right_edge[i] -
- (left_edge[min_index] - right_edge[min_index]))/2 +
- (orig_mid_min - mid_min);
-
- debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
- [%u]=%d\n", __func__, __LINE__, i, shift_dq);
-
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
- temp_dq_out1_delay = readl(addr + (i << 2));
- if (shift_dq + (int32_t)temp_dq_out1_delay >
- (int32_t)IO_IO_OUT1_DELAY_MAX) {
- shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
- } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
- shift_dq = -(int32_t)temp_dq_out1_delay;
- }
- debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
- i, shift_dq);
- scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
- scc_mgr_load_dq(i);
-
- debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
- left_edge[i] - shift_dq + (-mid_min),
- right_edge[i] + shift_dq - (-mid_min));
- /* To determine values for export structures */
- if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
- dq_margin = left_edge[i] - shift_dq + (-mid_min);
+ debug_cond(DLEVEL == 1,
+ "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
+ __func__, __LINE__, start_dqs, new_dqs, mid_min);
- if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
- dqs_margin = right_edge[i] + shift_dq - (-mid_min);
- }
+ /* Add delay to bring centre of all DQ windows to the same "level". */
+ center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min,
+ min_index, 0, &dq_margin, &dqs_margin);
/* Move DQS */
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
/*
- * set the left and right edge of each bit to an illegal value,
- * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
+ * Set the left and right edge of each bit to an illegal value.
+ * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
*/
- left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
- right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
- int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
- int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
- int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
- int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
- int32_t win_best = 0;
-
- /* Search for the/part of the window with DM shift */
- for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
- scc_mgr_apply_group_dm_out1_delay(d);
- writel(0, &sdr_scc_mgr->update);
+ left_edge[0] = iocfg->io_out1_delay_max + 1;
+ right_edge[0] = iocfg->io_out1_delay_max + 1;
- if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
- PASS_ALL_BITS, &bit_chk,
- 0)) {
- /* USE Set current end of the window */
- end_curr = -d;
- /*
- * If a starting edge of our window has not been seen
- * this is our current start of the DM window.
- */
- if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
- bgn_curr = -d;
+ /* Search for the/part of the window with DM shift. */
+ search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr,
+ &bgn_best, &end_best, &win_best, 0);
- /*
- * If current window is bigger than best seen.
- * Set best seen to be current window.
- */
- if ((end_curr-bgn_curr+1) > win_best) {
- win_best = end_curr-bgn_curr+1;
- bgn_best = bgn_curr;
- end_best = end_curr;
- }
- } else {
- /* We just saw a failing test. Reset temp edge */
- bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
- end_curr = IO_IO_OUT1_DELAY_MAX + 1;
- }
- }
-
-
- /* Reset DM delay chains to 0 */
+ /* Reset DM delay chains to 0. */
scc_mgr_apply_group_dm_out1_delay(0);
/*
* Check to see if the current window nudges up aganist 0 delay.
* If so we need to continue the search by shifting DQS otherwise DQS
- * search begins as a new search. */
+ * search begins as a new search.
+ */
if (end_curr != 0) {
- bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
- end_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ bgn_curr = iocfg->io_out1_delay_max + 1;
+ end_curr = iocfg->io_out1_delay_max + 1;
}
- /* Search for the/part of the window with DQS shifts */
- for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
- /*
- * Note: This only shifts DQS, so are we limiting ourselve to
- * width of DQ unnecessarily.
- */
- scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
- d + new_dqs);
-
- writel(0, &sdr_scc_mgr->update);
- if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
- PASS_ALL_BITS, &bit_chk,
- 0)) {
- /* USE Set current end of the window */
- end_curr = d;
- /*
- * If a beginning edge of our window has not been seen
- * this is our current begin of the DM window.
- */
- if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
- bgn_curr = d;
-
- /*
- * If current window is bigger than best seen. Set best
- * seen to be current window.
- */
- if ((end_curr-bgn_curr+1) > win_best) {
- win_best = end_curr-bgn_curr+1;
- bgn_best = bgn_curr;
- end_best = end_curr;
- }
- } else {
- /* We just saw a failing test. Reset temp edge */
- bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
- end_curr = IO_IO_OUT1_DELAY_MAX + 1;
-
- /* Early exit optimization: if ther remaining delay
- chain space is less than already seen largest window
- we can exit */
- if ((win_best-1) >
- (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
- break;
- }
- }
- }
+ /* Search for the/part of the window with DQS shifts. */
+ search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr,
+ &bgn_best, &end_best, &win_best, new_dqs);
- /* assign left and right edge for cal and reporting; */
- left_edge[0] = -1*bgn_best;
+ /* Assign left and right edge for cal and reporting. */
+ left_edge[0] = -1 * bgn_best;
right_edge[0] = end_best;
- debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
- __LINE__, left_edge[0], right_edge[0]);
+ debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n",
+ __func__, __LINE__, left_edge[0], right_edge[0]);
- /* Move DQS (back to orig) */
+ /* Move DQS (back to orig). */
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
/* Move DM */
- /* Find middle of window for the DM bit */
+ /* Find middle of window for the DM bit. */
mid = (left_edge[0] - right_edge[0]) / 2;
- /* only move right, since we are not moving DQS/DQ */
+ /* Only move right, since we are not moving DQS/DQ. */
if (mid < 0)
mid = 0;
- /* dm_marign should fail if we never find a window */
+ /* dm_marign should fail if we never find a window. */
if (win_best == 0)
dm_margin = -1;
else
scc_mgr_apply_group_dm_out1_delay(mid);
writel(0, &sdr_scc_mgr->update);
- debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
- dm_margin=%d\n", __func__, __LINE__, left_edge[0],
- right_edge[0], mid, dm_margin);
- /* Export values */
+ debug_cond(DLEVEL == 2,
+ "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
+ __func__, __LINE__, left_edge[0], right_edge[0],
+ mid, dm_margin);
+ /* Export values. */
gbl->fom_out += dq_margin + dqs_margin;
- debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
- dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
- dq_margin, dqs_margin, dm_margin);
+ debug_cond(DLEVEL == 2,
+ "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
+ __func__, __LINE__, dq_margin, dqs_margin, dm_margin);
/*
* Do not remove this line as it makes sure all of our
* decisions have been applied.
*/
writel(0, &sdr_scc_mgr->update);
- return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
+
+ if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0))
+ return -EINVAL;
+
+ return 0;
}
/**
reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
- if (!ret) {
+ if (ret)
set_failing_group_stage(group, CAL_STAGE_WRITES,
CAL_SUBSTAGE_WRITES_CENTER);
- return -EIO;
- }
- return 0;
+ return ret;
}
/**
{
int r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
- /* Test if the rank should be skipped. */
- if (param->skip_ranks[r])
- continue;
-
+ for (r = 0; r < rwcfg->mem_number_of_ranks; r++) {
/* Set rank. */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
/* Precharge all banks. */
- writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ writel(rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
+ writel(rwcfg->activate_0_and_1_wait1,
&sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
+ writel(rwcfg->activate_0_and_1_wait2,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* Activate rows. */
- writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
}
debug("%s:%d\n", __func__, __LINE__);
/* Need to update every shadow register set used by the interface */
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ for (r = 0; r < rwcfg->mem_number_of_ranks;
r += NUM_RANKS_PER_SHADOW_REG) {
/*
* Set output phase alignment settings appropriate for
* skip calibration.
*/
- for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
scc_mgr_set_dqs_en_phase(i, 0);
-#if IO_DLL_CHAIN_LENGTH == 6
- scc_mgr_set_dqdqs_output_phase(i, 6);
-#else
- scc_mgr_set_dqdqs_output_phase(i, 7);
-#endif
+ if (iocfg->dll_chain_length == 6)
+ scc_mgr_set_dqdqs_output_phase(i, 6);
+ else
+ scc_mgr_set_dqdqs_output_phase(i, 7);
/*
* Case:33398
*
*
* Hence, to make DQS aligned to CK, we need to delay
* DQS by:
- * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
+ * (720 - 90 - 180 - 2 * (360 / iocfg->dll_chain_length))
*
- * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
+ * Dividing the above by (360 / iocfg->dll_chain_length)
* gives us the number of ptaps, which simplies to:
*
- * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
+ * (1.25 * iocfg->dll_chain_length - 2)
*/
scc_mgr_set_dqdqs_output_phase(i,
- 1.25 * IO_DLL_CHAIN_LENGTH - 2);
+ 1.25 * iocfg->dll_chain_length - 2);
}
writel(0xff, &sdr_scc_mgr->dqs_ena);
writel(0xff, &sdr_scc_mgr->dqs_io_ena);
- for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) {
writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_GROUP_COUNTER_OFFSET);
}
}
/* Compensate for simulation model behaviour */
- for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
scc_mgr_set_dqs_bus_in_delay(i, 10);
scc_mgr_load_dqs(i);
}
uint32_t failing_groups = 0;
uint32_t group_failed = 0;
- const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width /
+ rwcfg->mem_if_write_dqs_width;
debug("%s:%d\n", __func__, __LINE__);
/* Initialize bit slips. */
mem_precharge_and_activate();
- for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_GROUP_COUNTER_OFFSET);
/* Only needed once to set all groups, pins, DQ, DQS, DM. */
*/
scc_mgr_zero_all();
- run_groups = ~param->skip_groups;
+ run_groups = ~0;
for (write_group = 0, write_test_bgn = 0; write_group
- < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
- write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
+ < rwcfg->mem_if_write_dqs_width; write_group++,
+ write_test_bgn += rwcfg->mem_dq_per_write_dqs) {
/* Initialize the group failure */
group_failed = 0;
read_test_bgn = 0;
read_group < (write_group + 1) * rwdqs_ratio;
read_group++,
- read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
+ read_test_bgn += rwcfg->mem_dq_per_read_dqs) {
if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
continue;
/* Calibrate the output side */
for (rank_bgn = 0, sr = 0;
- rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn < rwcfg->mem_number_of_ranks;
rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
continue;
if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
continue;
- /*
- * Determine if this set of ranks
- * should be skipped entirely.
- */
- if (param->skip_shadow_regs[sr])
- continue;
-
/* Calibrate WRITEs */
if (!rw_mgr_mem_calibrate_writes(rank_bgn,
write_group, write_test_bgn))
read_test_bgn = 0;
read_group < (write_group + 1) * rwdqs_ratio;
read_group++,
- read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
+ read_test_bgn += rwcfg->mem_dq_per_read_dqs) {
if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
continue;
- if (rw_mgr_mem_calibrate_vfifo_end(read_group,
+ if (!rw_mgr_mem_calibrate_vfifo_end(read_group,
read_test_bgn))
continue;
if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
continue;
- /*
- * If we're skipping groups as part of debug,
- * don't calibrate LFIFO.
- */
- if (param->skip_groups != 0)
- continue;
-
/* Calibrate the LFIFO */
if (!rw_mgr_mem_calibrate_lfifo())
return 0;
*/
static void hc_initialize_rom_data(void)
{
+ unsigned int nelem = 0;
+ const u32 *rom_init;
u32 i, addr;
+ socfpga_get_seq_inst_init(&rom_init, &nelem);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
- for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
- writel(inst_rom_init[i], addr + (i << 2));
+ for (i = 0; i < nelem; i++)
+ writel(rom_init[i], addr + (i << 2));
+ socfpga_get_seq_ac_init(&rom_init, &nelem);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
- for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
- writel(ac_rom_init[i], addr + (i << 2));
+ for (i = 0; i < nelem; i++)
+ writel(rom_init[i], addr + (i << 2));
}
/**
* Compute usable version of value in case we skip full
* computation later.
*/
- writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
+ writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap) - 1,
&sdr_reg_file->dtaps_per_ptap);
/* trk_sample_count */
&sdr_reg_file->delays);
/* mux delay */
- writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
- (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
+ writel((rwcfg->idle << 24) | (rwcfg->activate_1 << 16) |
+ (rwcfg->sgle_read << 8) | (rwcfg->precharge_all << 0),
&sdr_reg_file->trk_rw_mgr_addr);
- writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
+ writel(rwcfg->mem_if_read_dqs_width,
&sdr_reg_file->trk_read_dqs_width);
/* trefi [7:0] */
- writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
+ writel((rwcfg->refresh_all << 24) | (1000 << 0),
&sdr_reg_file->trk_rfsh);
}
param = &my_param;
gbl = &my_gbl;
+ rwcfg = socfpga_get_sdram_rwmgr_config();
+ iocfg = socfpga_get_sdram_io_config();
+ misccfg = socfpga_get_sdram_misc_config();
+
/* Set the calibration enabled by default */
gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
/*
debug("%s:%d\n", __func__, __LINE__);
debug_cond(DLEVEL == 1,
"DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
- RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
- RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
+ rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm,
+ rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs,
+ rwcfg->mem_virtual_groups_per_read_dqs,
+ rwcfg->mem_virtual_groups_per_write_dqs);
debug_cond(DLEVEL == 1,
"dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
- RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
- RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
- IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
+ rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width,
+ rwcfg->mem_data_width, rwcfg->mem_data_mask_width,
+ iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap);
debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
+ iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length);
debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
- IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
- IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
+ iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max,
+ iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max);
debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
- IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
- IO_IO_OUT2_DELAY_MAX);
+ iocfg->io_in_delay_max, iocfg->io_out1_delay_max,
+ iocfg->io_out2_delay_max);
debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
- IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
+ iocfg->dqs_in_reserve, iocfg->dqs_out_reserve);
hc_initialize_rom_data();