* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
* b = 6A
*/
- rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
- SEQ_TINIT_CNTR2_VAL,
+ rw_mgr_mem_init_load_regs(TINIT_CNTR0_VAL, TINIT_CNTR1_VAL,
+ TINIT_CNTR2_VAL,
rwcfg->init_reset_0_cke_0);
/* Indicate that memory is stable. */
* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
* b = FF
*/
- rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
- SEQ_TRESET_CNTR2_VAL,
+ rw_mgr_mem_init_load_regs(TRESET_CNTR0_VAL, TRESET_CNTR1_VAL,
+ TRESET_CNTR2_VAL,
rwcfg->init_reset_1_cke_0);
/* Bring up clock enable. */
{
u32 i;
- for (i = 0; i < VFIFO_SIZE - 1; i++)
+ for (i = 0; i < READ_VALID_FIFO_SIZE - 1; i++)
rw_mgr_incr_vfifo(grp);
}
{
u32 v, ret, fail_cnt = 0;
- for (v = 0; v < VFIFO_SIZE; v++) {
+ for (v = 0; v < READ_VALID_FIFO_SIZE; v++) {
debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
__func__, __LINE__, v);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
static int sdr_find_phase(int working, const u32 grp, u32 *work,
u32 *i, u32 *p)
{
- const u32 end = VFIFO_SIZE + (working ? 0 : 1);
+ const u32 end = READ_VALID_FIFO_SIZE + (working ? 0 : 1);
int ret;
for (; *i < end; (*i)++) {
* push vfifo until we can successfully calibrate. We can do this
* because the largest possible margin in 1 VFIFO cycle.
*/
- for (i = 0; i < VFIFO_SIZE; i++) {
+ for (i = 0; i < READ_VALID_FIFO_SIZE; i++) {
debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,