ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL

[oweals/u-boot.git] / drivers / ddr / altera / sequencer.c

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 4596f552b3519e33e0311d8ad3c5c99776fe4094..f6414e02c7483e4da3827db4ce2e079088a38a88 100644 (file)
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -43,6 +43,7 @@ static struct socfpga_sdr_ctrl *sdr_ctrl =
 
 const struct socfpga_sdram_rw_mgr_config *rwcfg;
 const struct socfpga_sdram_io_config *iocfg;
+const struct socfpga_sdram_misc_config *misccfg;
 
 #define DELTA_D                1
 
@@ -965,8 +966,8 @@ static void rw_mgr_mem_initialize(void)
         * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
         * b = 6A
         */
-       rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
-                                 SEQ_TINIT_CNTR2_VAL,
+       rw_mgr_mem_init_load_regs(TINIT_CNTR0_VAL, TINIT_CNTR1_VAL,
+                                 TINIT_CNTR2_VAL,
                                  rwcfg->init_reset_0_cke_0);
 
        /* Indicate that memory is stable. */
@@ -986,8 +987,8 @@ static void rw_mgr_mem_initialize(void)
         * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
         * b = FF
         */
-       rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
-                                 SEQ_TRESET_CNTR2_VAL,
+       rw_mgr_mem_init_load_regs(TRESET_CNTR0_VAL, TRESET_CNTR1_VAL,
+                                 TRESET_CNTR2_VAL,
                                  rwcfg->init_reset_1_cke_0);
 
        /* Bring up clock enable. */
@@ -1506,7 +1507,7 @@ static void rw_mgr_decr_vfifo(const u32 grp)
 {
        u32 i;
 
-       for (i = 0; i < VFIFO_SIZE - 1; i++)
+       for (i = 0; i < READ_VALID_FIFO_SIZE - 1; i++)
                rw_mgr_incr_vfifo(grp);
 }
 
@@ -1520,7 +1521,7 @@ static int find_vfifo_failing_read(const u32 grp)
 {
        u32 v, ret, fail_cnt = 0;
 
-       for (v = 0; v < VFIFO_SIZE; v++) {
+       for (v = 0; v < READ_VALID_FIFO_SIZE; v++) {
                debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
                           __func__, __LINE__, v);
                ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
@@ -1591,7 +1592,7 @@ static int sdr_find_phase_delay(int working, int delay, const u32 grp,
 static int sdr_find_phase(int working, const u32 grp, u32 *work,
                          u32 *i, u32 *p)
 {
-       const u32 end = VFIFO_SIZE + (working ? 0 : 1);
+       const u32 end = READ_VALID_FIFO_SIZE + (working ? 0 : 1);
        int ret;
 
        for (; *i < end; (*i)++) {
@@ -1772,7 +1773,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
         * push vfifo until we can successfully calibrate. We can do this
         * because the largest possible margin in 1 VFIFO cycle.
         */
-       for (i = 0; i < VFIFO_SIZE; i++) {
+       for (i = 0; i < READ_VALID_FIFO_SIZE; i++) {
                debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
                if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
                                                             PASS_ONE_BIT,
@@ -3700,6 +3701,7 @@ int sdram_calibration_full(void)
 
        rwcfg = socfpga_get_sdram_rwmgr_config();
        iocfg = socfpga_get_sdram_io_config();
+       misccfg = socfpga_get_sdram_misc_config();
 
        /* Set the calibration enabled by default */
        gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;