*/
}
-/*
- * performs a guaranteed read on the patterns we are going to use during a
- * read test to ensure memory works
+/**
+ * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
+ * @rank_bgn: Rank number
+ * @group: Read/Write Group
+ * @all_ranks: Test all ranks
+ *
+ * Performs a guaranteed read on the patterns we are going to use during a
+ * read test to ensure memory works.
*/
-static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
- uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
- uint32_t all_ranks)
+static int
+rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
+ const u32 all_ranks)
{
- uint32_t r, vg;
- uint32_t correct_mask_vg;
- uint32_t tmp_bit_chk;
- uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
- (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- uint32_t addr;
- uint32_t base_rw_mgr;
+ const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ const u32 addr_offset =
+ (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
+ const u32 rank_end = all_ranks ?
+ RW_MGR_MEM_NUMBER_OF_RANKS :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ const u32 correct_mask_vg = param->read_correct_mask_vg;
- *bit_chk = param->read_correct_mask;
- correct_mask_vg = param->read_correct_mask_vg;
+ u32 tmp_bit_chk, base_rw_mgr, bit_chk;
+ int vg, r;
+ int ret = 0;
+
+ bit_chk = param->read_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
+ /* Request to skip the rank */
if (param->skip_ranks[r])
- /* request to skip the rank */
continue;
- /* set rank */
+ /* Set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts of read commands */
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
tmp_bit_chk = 0;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
- /* reset the fifos to get pointers to known state */
-
+ for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
+ vg >= 0; vg--) {
+ /* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RESET_READ_DATAPATH_OFFSET);
-
- tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
- / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
-
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_GUARANTEED_READ, addr +
- ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
- vg) << 2));
+ writel(RW_MGR_GUARANTEED_READ,
+ addr + addr_offset + (vg << 2));
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
- tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
-
- if (vg == 0)
- break;
+ tmp_bit_chk <<= shift_ratio;
+ tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
}
- *bit_chk &= tmp_bit_chk;
+
+ bit_chk &= tmp_bit_chk;
}
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
- %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
- (long unsigned int)(*bit_chk == param->read_correct_mask));
- return *bit_chk == param->read_correct_mask;
+
+ if (bit_chk != param->read_correct_mask)
+ ret = -EIO;
+
+ debug_cond(DLEVEL == 1,
+ "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
+ __func__, __LINE__, group, bit_chk,
+ param->read_correct_mask, ret);
+
+ return ret;
}
/**
}
}
-static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
- uint32_t dtaps_per_ptap, uint32_t *work_bgn,
- uint32_t *v, uint32_t *d, uint32_t *p,
- uint32_t *i, uint32_t *max_working_cnt)
+/**
+ * sdr_find_phase() - Find DQS enable phase
+ * @working: If 1, look for working phase, if 0, look for non-working phase
+ * @grp: Read/Write group
+ * @v: VFIFO value
+ * @work: Working window position
+ * @i: Iterator
+ * @p: DQS Phase Iterator
+ *
+ * Find working or non-working DQS enable phase setting.
+ */
+static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
+ u32 *i, u32 *p)
{
- uint32_t found_begin = 0;
- uint32_t tmp_delay = 0;
- uint32_t test_status;
+ u32 ret, bit_chk;
+ const u32 end = VFIFO_SIZE + (working ? 0 : 1);
- for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
- *work_bgn = tmp_delay;
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
+ for (; *i < end; (*i)++) {
+ if (working)
+ *p = 0;
- for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
- for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
- IO_DELAY_PER_OPA_TAP) {
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
+ for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++) {
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
- test_status =
- rw_mgr_mem_calibrate_read_test_all_ranks
- (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
+ ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT, &bit_chk, 0);
+ if (!working)
+ ret = !ret;
- if (test_status) {
- *max_working_cnt = 1;
- found_begin = 1;
- break;
- }
- }
-
- if (found_begin)
- break;
+ if (ret)
+ return 0;
- if (*p > IO_DQS_EN_PHASE_MAX)
- /* fiddle with FIFO */
- rw_mgr_incr_vfifo(*grp, v);
+ *work += IO_DELAY_PER_OPA_TAP;
}
- if (found_begin)
- break;
+ if (*p > IO_DQS_EN_PHASE_MAX) {
+ /* Fiddle with FIFO. */
+ rw_mgr_incr_vfifo(grp, v);
+ if (!working)
+ *p = 0;
+ }
}
- if (*i >= VFIFO_SIZE) {
- /* cannot find working solution */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
- ptap/dtap\n", __func__, __LINE__);
- return 0;
- } else {
- return 1;
+ return -EINVAL;
+}
+
+static int sdr_working_phase(uint32_t grp, uint32_t *work_bgn,
+ uint32_t *v, uint32_t *d, uint32_t *p,
+ uint32_t *i)
+{
+ const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ int ret;
+
+ *work_bgn = 0;
+
+ for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
+ *i = 0;
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
+ ret = sdr_find_phase(1, grp, v, work_bgn, i, p);
+ if (!ret)
+ return 0;
+ *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
}
+
+ /* Cannot find working solution */
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
+ __func__, __LINE__);
+ return -EINVAL;
}
-static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
+static void sdr_backup_phase(uint32_t grp,
uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *max_working_cnt)
+ uint32_t *p)
{
- uint32_t found_begin = 0;
uint32_t tmp_delay;
+ u32 bit_chk;
/* Special case code for backing up a phase */
if (*p == 0) {
*p = IO_DQS_EN_PHASE_MAX;
- rw_mgr_decr_vfifo(*grp, v);
+ rw_mgr_decr_vfifo(grp, v);
} else {
(*p)--;
}
tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
(*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
- if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
+ if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
- bit_chk, 0)) {
- found_begin = 1;
+ &bit_chk, 0)) {
*work_bgn = tmp_delay;
break;
}
}
- /* We have found a working dtap before the ptap found above */
- if (found_begin == 1)
- (*max_working_cnt)++;
-
/*
* Restore VFIFO to old state before we decremented it
* (if needed).
(*p)++;
if (*p > IO_DQS_EN_PHASE_MAX) {
*p = 0;
- rw_mgr_incr_vfifo(*grp, v);
+ rw_mgr_incr_vfifo(grp, v);
}
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
}
-static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
+static int sdr_nonworking_phase(uint32_t grp,
uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
+ uint32_t *p, uint32_t *i,
uint32_t *work_end)
{
- uint32_t found_end = 0;
+ int ret;
(*p)++;
*work_end += IO_DELAY_PER_OPA_TAP;
if (*p > IO_DQS_EN_PHASE_MAX) {
- /* fiddle with FIFO */
+ /* Fiddle with FIFO. */
*p = 0;
- rw_mgr_incr_vfifo(*grp, v);
+ rw_mgr_incr_vfifo(grp, v);
}
- for (; *i < VFIFO_SIZE + 1; (*i)++) {
- for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
- += IO_DELAY_PER_OPA_TAP) {
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
-
- if (!rw_mgr_mem_calibrate_read_test_all_ranks
- (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
- found_end = 1;
- break;
- } else {
- (*max_working_cnt)++;
- }
- }
-
- if (found_end)
- break;
-
- if (*p > IO_DQS_EN_PHASE_MAX) {
- /* fiddle with FIFO */
- rw_mgr_incr_vfifo(*grp, v);
- *p = 0;
- }
+ ret = sdr_find_phase(0, grp, v, work_end, i, p);
+ if (ret) {
+ /* Cannot see edge of failing read. */
+ debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
+ __func__, __LINE__);
}
- if (*i >= VFIFO_SIZE + 1) {
- /* cannot see edge of failing read */
- debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
- failed\n", __func__, __LINE__);
- return 0;
- } else {
- return 1;
- }
+ return ret;
}
-static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
- uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *work_mid,
- uint32_t *work_end)
+/**
+ * sdr_find_window_center() - Find center of the working DQS window.
+ * @grp: Read/Write group
+ * @work_bgn: First working settings
+ * @work_end: Last working settings
+ * @val: VFIFO value
+ *
+ * Find center of the working DQS enable window.
+ */
+static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
+ const u32 work_end, const u32 val)
{
- int i;
+ u32 bit_chk, work_mid, v = val;
int tmp_delay = 0;
+ int i, p, d;
- *work_mid = (*work_bgn + *work_end) / 2;
+ work_mid = (work_bgn + work_end) / 2;
debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
- *work_bgn, *work_end, *work_mid);
+ work_bgn, work_end, work_mid);
/* Get the middle delay to be less than a VFIFO delay */
- for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
- (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
- ;
+ tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
+
debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
- while (*work_mid > tmp_delay)
- *work_mid -= tmp_delay;
- debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
+ work_mid %= tmp_delay;
+ debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
- tmp_delay = 0;
- for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
- (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
- ;
- tmp_delay -= IO_DELAY_PER_OPA_TAP;
- debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
- for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
- tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
- ;
- debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
+ tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
+ if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
+ tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
+ p = tmp_delay / IO_DELAY_PER_OPA_TAP;
+
+ debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
+
+ d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
+ if (d > IO_DQS_EN_DELAY_MAX)
+ d = IO_DQS_EN_DELAY_MAX;
+ tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
+ debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
+
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
/*
* push vfifo until we can successfully calibrate. We can do this
*/
for (i = 0; i < VFIFO_SIZE; i++) {
debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
- *v);
- if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
+ v);
+ if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
- bit_chk, 0)) {
- break;
+ &bit_chk, 0)) {
+ debug_cond(DLEVEL == 2,
+ "%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
+ __func__, __LINE__, v, p, d);
+ return 0;
}
- /* fiddle with FIFO */
- rw_mgr_incr_vfifo(*grp, v);
+ /* Fiddle with FIFO. */
+ rw_mgr_incr_vfifo(grp, &v);
}
- if (i >= VFIFO_SIZE) {
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
- failed\n", __func__, __LINE__);
- return 0;
- } else {
- return 1;
- }
+ debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
+ __func__, __LINE__);
+ return -EINVAL;
}
/* find a good dqs enable to use */
static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
{
uint32_t v, d, p, i;
- uint32_t max_working_cnt;
uint32_t bit_chk;
uint32_t dtaps_per_ptap;
- uint32_t work_bgn, work_mid, work_end;
+ uint32_t work_bgn, work_end;
uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
debug("%s:%d %u\n", __func__, __LINE__, grp);
/* * Step 1 : First push vfifo until we get a failing read * */
v = find_vfifo_read(grp, &bit_chk);
- max_working_cnt = 0;
-
/* ******************************************************** */
/* * step 2: find first working phase, increment in ptaps * */
work_bgn = 0;
- if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
- &p, &i, &max_working_cnt) == 0)
+ if (sdr_working_phase(grp, &work_bgn, &v, &d, &p, &i))
return 0;
work_end = work_bgn;
/* * step 3a: if we have room, back off by one and
increment in dtaps * */
- sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
- &max_working_cnt);
+ sdr_backup_phase(grp, &work_bgn, &v, &d, &p);
/* ********************************************************* */
/* * step 4a: go forward from working phase to non working
phase, increment in ptaps * */
- if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
- &i, &max_working_cnt, &work_end) == 0)
+ if (sdr_nonworking_phase(grp, &work_bgn, &v, &d, &p,
+ &i, &work_end))
return 0;
/* ********************************************************* */
v, p, d, work_bgn);
work_end = work_bgn;
-
- /* * The actual increment of dtaps is done outside of the
- if/else loop to share code */
-
- /* Only here to counterbalance a subtract later on which is
- not needed if this branch of the algorithm is taken */
- max_working_cnt++;
}
/* The dtap increment to find the failing edge is done here */
/* ******************************************** */
/* * step 6: Find the centre of the window * */
- if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
- &work_mid, &work_end) == 0)
- return 0;
+ if (sdr_find_window_centre(grp, work_bgn, work_end, v))
+ return 0; /* FIXME: Old code, return 0 means failure :-( */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
- vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
- v, p-1, d);
return 1;
}
-/*
- * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
- * dq_in_delay values
- */
-static uint32_t
-rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
-(uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
-{
- uint32_t found;
- uint32_t i;
- uint32_t p;
- uint32_t d;
- uint32_t r;
-
- const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
- (RW_MGR_MEM_DQ_PER_READ_DQS-1);
- /* we start at zero, so have one less dq to devide among */
-
- debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
- test_bgn);
-
- /* try different dq_in_delays since the dq path is shorter than dqs */
-
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
- debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
- vfifo_find_dqs_", __func__, __LINE__);
- debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
- write_group, read_group);
- debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
- scc_mgr_set_dq_in_delay(p, d);
- scc_mgr_load_dq(p);
- }
- writel(0, &sdr_scc_mgr->update);
- }
-
- found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
-
- debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
- en_phase_sweep_dq", __func__, __LINE__);
- debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
- chain to zero\n", write_group, read_group, found);
-
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
- i++, p++) {
- scc_mgr_set_dq_in_delay(p, 0);
- scc_mgr_load_dq(p);
- }
- writel(0, &sdr_scc_mgr->update);
- }
-
- return found;
-}
-
/* per-bit deskew DQ and center */
static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
const u32 phase)
{
- u32 bit_chk;
int ret;
/* Set a particular DQ/DQS phase. */
* Altera EMI_RM 2015.05.04 :: Figure 1-26
* Back-to-Back reads of the patterns used for calibration.
*/
- ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1,
- &bit_chk, 1);
- if (!ret) { /* FIXME: 0 means failure in this old code :-( */
+ ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
+ if (ret)
debug_cond(DLEVEL == 1,
"%s:%d Guaranteed read test failed: g=%u p=%u\n",
__func__, __LINE__, rw_group, phase);
- return -EIO;
- }
-
- return 0;
+ return ret;
}
/**
static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
const u32 test_bgn)
{
- int ret;
-
/*
* Altera EMI_RM 2015.05.04 :: Figure 1-27
* DQS and DQS Eanble Signal Relationships.
*/
- ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(
- rw_group, rw_group, test_bgn);
- if (!ret) /* FIXME: 0 means failure in this old code :-( */
- return -EIO;
+
+ /* We start at zero, so have one less dq to devide among */
+ const u32 delay_step = IO_IO_IN_DELAY_MAX /
+ (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
+ int found;
+ u32 i, p, d, r;
+
+ debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
+
+ /* Try different dq_in_delays since the DQ path is shorter than DQS. */
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ for (i = 0, p = test_bgn, d = 0;
+ i < RW_MGR_MEM_DQ_PER_READ_DQS;
+ i++, p++, d += delay_step) {
+ debug_cond(DLEVEL == 1,
+ "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
+ __func__, __LINE__, rw_group, r, i, p, d);
+
+ scc_mgr_set_dq_in_delay(p, d);
+ scc_mgr_load_dq(p);
+ }
+
+ writel(0, &sdr_scc_mgr->update);
+ }
+
+ /*
+ * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
+ * dq_in_delay values
+ */
+ found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
+
+ debug_cond(DLEVEL == 1,
+ "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
+ __func__, __LINE__, rw_group, found);
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
+ writel(0, &sdr_scc_mgr->update);
+ }
+
+ if (!found)
+ return -EINVAL;
return 0;
+
}
/**
projects / oweals / u-boot.git / blobdiff