* @work: Working window position
* @i: Iterator
* @p: DQS Phase Iterator
- * @max_working_cnt: Counter
*
* Find working or non-working DQS enable phase setting.
*/
static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
- u32 *i, u32 *p, u32 *max_working_cnt)
+ u32 *i, u32 *p)
{
u32 ret, bit_chk;
const u32 end = VFIFO_SIZE + (working ? 0 : 1);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT, &bit_chk, 0);
- if (ret)
- (*max_working_cnt)++;
-
if (!working)
ret = !ret;
return -EINVAL;
}
-static int sdr_working_phase(uint32_t grp,
- uint32_t dtaps_per_ptap, uint32_t *work_bgn,
- uint32_t *v, uint32_t *d, uint32_t *p,
- uint32_t *i, uint32_t *max_working_cnt)
+static int sdr_working_phase(uint32_t grp, uint32_t *work_bgn,
+ uint32_t *v, uint32_t *d, uint32_t *p,
+ uint32_t *i)
{
+ const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
int ret;
*work_bgn = 0;
for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
*i = 0;
scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
- ret = sdr_find_phase(1, grp, v, work_bgn, i, p, max_working_cnt);
+ ret = sdr_find_phase(1, grp, v, work_bgn, i, p);
if (!ret)
return 0;
*work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
static void sdr_backup_phase(uint32_t grp,
uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *max_working_cnt)
+ uint32_t *p)
{
- uint32_t found_begin = 0;
uint32_t tmp_delay;
u32 bit_chk;
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
&bit_chk, 0)) {
- found_begin = 1;
*work_bgn = tmp_delay;
break;
}
}
- /* We have found a working dtap before the ptap found above */
- if (found_begin == 1)
- (*max_working_cnt)++;
-
/*
* Restore VFIFO to old state before we decremented it
* (if needed).
static int sdr_nonworking_phase(uint32_t grp,
uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
+ uint32_t *p, uint32_t *i,
uint32_t *work_end)
{
int ret;
rw_mgr_incr_vfifo(grp, v);
}
- ret = sdr_find_phase(0, grp, v, work_end, i, p, max_working_cnt);
+ ret = sdr_find_phase(0, grp, v, work_end, i, p);
if (ret) {
/* Cannot see edge of failing read. */
debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
{
uint32_t v, d, p, i;
- uint32_t max_working_cnt;
uint32_t bit_chk;
uint32_t dtaps_per_ptap;
uint32_t work_bgn, work_end;
/* * Step 1 : First push vfifo until we get a failing read * */
v = find_vfifo_read(grp, &bit_chk);
- max_working_cnt = 0;
-
/* ******************************************************** */
/* * step 2: find first working phase, increment in ptaps * */
work_bgn = 0;
- if (sdr_working_phase(grp, dtaps_per_ptap, &work_bgn, &v, &d,
- &p, &i, &max_working_cnt))
+ if (sdr_working_phase(grp, &work_bgn, &v, &d, &p, &i))
return 0;
work_end = work_bgn;
/* * step 3a: if we have room, back off by one and
increment in dtaps * */
- sdr_backup_phase(grp, &work_bgn, &v, &d, &p,
- &max_working_cnt);
+ sdr_backup_phase(grp, &work_bgn, &v, &d, &p);
/* ********************************************************* */
/* * step 4a: go forward from working phase to non working
phase, increment in ptaps * */
if (sdr_nonworking_phase(grp, &work_bgn, &v, &d, &p,
- &i, &max_working_cnt, &work_end))
+ &i, &work_end))
return 0;
/* ********************************************************* */
v, p, d, work_bgn);
work_end = work_bgn;
-
- /* * The actual increment of dtaps is done outside of the
- if/else loop to share code */
-
- /* Only here to counterbalance a subtract later on which is
- not needed if this branch of the algorithm is taken */
- max_working_cnt++;
}
/* The dtap increment to find the failing edge is done here */