+// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier: BSD-3-Clause
*/
#include <common.h>
#include "sequencer.h"
static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
- (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
-
+ (struct socfpga_sdr_rw_load_manager *)
+ (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
- (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
-
+ (struct socfpga_sdr_rw_load_jump_manager *)
+ (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
static struct socfpga_sdr_reg_file *sdr_reg_file =
(struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
-
static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
- (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
-
+ (struct socfpga_sdr_scc_mgr *)
+ (SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
(struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
-
static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
- (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
-
+ (struct socfpga_phy_mgr_cfg *)
+ (SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
static struct socfpga_data_mgr *data_mgr =
(struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
-
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
STATIC_SKIP_DELAY_LOOPS)
/* calibration steps requested by the rtl */
-uint16_t dyn_calib_steps;
+static u16 dyn_calib_steps;
/*
* To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
* zero when skipping
*/
-uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
+static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
((non_skip_value) & skip_delay_mask)
-struct gbl_type *gbl;
-struct param_type *param;
+static struct gbl_type *gbl;
+static struct param_type *param;
-static void set_failing_group_stage(uint32_t group, uint32_t stage,
- uint32_t substage)
+static void set_failing_group_stage(u32 group, u32 stage,
+ u32 substage)
{
/*
* Only set the global stage if there was not been any other
int i;
for (i = 0; i < 16; i++) {
- debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
+ debug_cond(DLEVEL >= 1, "%s:%d: Clearing SCC RFILE index %u\n",
__func__, __LINE__, i);
- scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
+ scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
}
}
-static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
+static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase)
{
scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
}
-static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
+static void scc_mgr_set_dqs_bus_in_delay(u32 read_group, u32 delay)
{
scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
}
-static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
+static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase)
{
scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
}
-static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
+static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay)
{
scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
}
-static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
+static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
+{
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
+}
+
+static void scc_mgr_set_dqs_io_in_delay(u32 delay)
{
scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
delay);
}
-static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
+static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay)
{
- scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
+ rwcfg->mem_dq_per_write_dqs + 1 + dm,
+ delay);
}
-static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
+static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay)
{
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
}
-static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
+static void scc_mgr_set_dqs_out1_delay(u32 delay)
{
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
delay);
}
-static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
+static void scc_mgr_set_dm_out1_delay(u32 dm, u32 delay)
{
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
rwcfg->mem_dq_per_write_dqs + 1 + dm,
}
/* load up dqs config settings */
-static void scc_mgr_load_dqs(uint32_t dqs)
+static void scc_mgr_load_dqs(u32 dqs)
{
writel(dqs, &sdr_scc_mgr->dqs_ena);
}
}
/* load up dq config settings */
-static void scc_mgr_load_dq(uint32_t dq_in_group)
+static void scc_mgr_load_dq(u32 dq_in_group)
{
writel(dq_in_group, &sdr_scc_mgr->dq_ena);
}
/* load up dm config settings */
-static void scc_mgr_load_dm(uint32_t dm)
+static void scc_mgr_load_dm(u32 dm)
{
writel(dm, &sdr_scc_mgr->dm_ena);
}
read_group, phase, 0);
}
-static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
- uint32_t phase)
+static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group,
+ u32 phase)
{
/*
* USER although the h/w doesn't support different phases per
write_group, phase, 0);
}
-static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
- uint32_t delay)
+static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group,
+ u32 delay)
{
/*
* In shadow register mode, the T11 settings are stored in
*/
scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
read_group, delay, 1);
- writel(0, &sdr_scc_mgr->update);
}
/**
SCC_MGR_HHP_GLOBALS_OFFSET |
SCC_MGR_HHP_EXTRAS_OFFSET;
- debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
+ debug_cond(DLEVEL >= 1, "%s:%d Setting HHP Extras\n",
__func__, __LINE__);
writel(value, addr);
- debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
+ debug_cond(DLEVEL >= 1, "%s:%d Done Setting HHP Extras\n",
__func__, __LINE__);
}
writel(0xff, &sdr_scc_mgr->dq_ena);
/* Zero all DM config settings. */
- for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
+ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
+ if (!out_only)
+ scc_mgr_set_dm_in_delay(i, 0);
scc_mgr_set_dm_out1_delay(i, 0);
+ }
/* Multicast to all DM enables. */
writel(0xff, &sdr_scc_mgr->dm_ena);
* apply and load a particular input delay for the DQ pins in a group
* group_bgn is the index of the first dq pin (in the write group)
*/
-static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
+static void scc_mgr_apply_group_dq_in_delay(u32 group_bgn, u32 delay)
{
- uint32_t i, p;
+ u32 i, p;
for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) {
scc_mgr_set_dq_in_delay(p, delay);
}
/* apply and load a particular output delay for the DM pins in a group */
-static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
+static void scc_mgr_apply_group_dm_out1_delay(u32 delay1)
{
- uint32_t i;
+ u32 i;
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
scc_mgr_set_dm_out1_delay(i, delay1);
/* apply and load delay on both DQS and OCT out1 */
-static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
- uint32_t delay)
+static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 write_group,
+ u32 delay)
{
scc_mgr_set_dqs_out1_delay(delay);
scc_mgr_load_dqs_io();
/* DQS shift */
new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
if (new_delay > iocfg->io_out2_delay_max) {
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
__func__, __LINE__, write_group, delay, new_delay,
iocfg->io_out2_delay_max,
/* OCT shift */
new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
if (new_delay > iocfg->io_out2_delay_max) {
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
__func__, __LINE__, write_group, delay,
new_delay, iocfg->io_out2_delay_max,
*/
if (afi_clocks < 0x100) {
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
- &sdr_rw_load_mgr_regs->load_cntr1);
+ &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->idle_loop1,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
- &sdr_rw_load_mgr_regs->load_cntr0);
+ &sdr_rw_load_mgr_regs->load_cntr0);
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
- &sdr_rw_load_mgr_regs->load_cntr1);
+ &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->idle_loop2,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(rwcfg->idle_loop2,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
do {
writel(rwcfg->idle_loop2,
- SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RUN_SINGLE_GROUP_OFFSET);
+ SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} while (c_loop-- != 0);
}
debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
*/
static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
{
- uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET;
/* Load counters */
* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
* b = 6A
*/
- rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val, misccfg->tinit_cntr1_val,
+ rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val,
+ misccfg->tinit_cntr1_val,
misccfg->tinit_cntr2_val,
rwcfg->init_reset_0_cke_0);
* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
* b = FF
*/
- rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val, misccfg->treset_cntr1_val,
+ rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val,
+ misccfg->treset_cntr1_val,
misccfg->treset_cntr2_val,
rwcfg->init_reset_1_cke_0);
} else {
mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1;
writel(rwcfg->lfsr_wr_rd_bank_0_data,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(rwcfg->lfsr_wr_rd_bank_0_nop,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
} else if (rw_wl_nop_cycles == 0) {
/*
} else {
mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
writel(rwcfg->lfsr_wr_rd_bank_0_dqs,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
}
} else {
/*
if (test_dm) {
mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
writel(rwcfg->lfsr_wr_rd_bank_0_nop,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
}
if (test_dm) {
writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
} else {
writel(rwcfg->lfsr_wr_rd_bank_0_wait,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
}
writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS |
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
if (all_correct) {
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"write_test(%u,%u,ALL) : %u == %u => %i\n",
write_group, use_dm, *bit_chk,
param->write_correct_mask,
*bit_chk == param->write_correct_mask);
return *bit_chk == param->write_correct_mask;
} else {
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"write_test(%u,%u,ONE) : %u != %i => %i\n",
write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
return *bit_chk != 0x00;
/* Load up a constant bursts of read commands */
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
writel(rwcfg->guaranteed_read,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->guaranteed_read_cont,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
tmp_bit_chk = 0;
for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1;
if (bit_chk != param->read_correct_mask)
ret = -EIO;
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
__func__, __LINE__, group, bit_chk,
param->read_correct_mask, ret);
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
writel(rwcfg->guaranteed_write_wait0,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->guaranteed_write_wait1,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
writel(rwcfg->guaranteed_write_wait2,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
writel(rwcfg->guaranteed_write_wait3,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->read_b2b_wait1,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
writel(rwcfg->read_b2b_wait2,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
if (quick_read_mode)
writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
writel(rwcfg->read_b2b,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
if (all_groups)
writel(rwcfg->mem_if_read_dqs_width *
rwcfg->mem_virtual_groups_per_read_dqs - 1,
writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
writel(rwcfg->read_b2b,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
tmp_bit_chk = 0;
for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0;
}
writel(rwcfg->read_b2b, addr +
- ((group * rwcfg->mem_virtual_groups_per_read_dqs +
- vg) << 2));
+ ((group *
+ rwcfg->mem_virtual_groups_per_read_dqs +
+ vg) << 2));
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs /
if (all_correct) {
ret = (*bit_chk == param->read_correct_mask);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
__func__, __LINE__, group, all_groups, *bit_chk,
param->read_correct_mask, ret);
} else {
ret = (*bit_chk != 0x00);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
__func__, __LINE__, group, all_groups, *bit_chk,
0, ret);
u32 v, ret, fail_cnt = 0;
for (v = 0; v < misccfg->read_valid_fifo_size; v++) {
- debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
+ debug_cond(DLEVEL >= 2, "%s:%d: vfifo %u\n",
__func__, __LINE__, v);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT, 0);
}
/* No failing read found! Something must have gone wrong. */
- debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
+ debug_cond(DLEVEL >= 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
return 0;
}
static int sdr_find_phase_delay(int working, int delay, const u32 grp,
u32 *work, const u32 work_inc, u32 *pd)
{
- const u32 max = delay ? iocfg->dqs_en_delay_max : iocfg->dqs_en_phase_max;
+ const u32 max = delay ? iocfg->dqs_en_delay_max :
+ iocfg->dqs_en_phase_max;
u32 ret;
for (; *pd <= max; (*pd)++) {
}
/* Cannot find working solution */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
+ debug_cond(DLEVEL >= 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
__func__, __LINE__);
return -EINVAL;
}
tmp_delay = *work_bgn - iocfg->delay_per_opa_tap;
scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
- for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn; d++) {
+ for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn;
+ d++) {
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
ret = sdr_find_phase(0, grp, work_end, i, p);
if (ret) {
/* Cannot see edge of failing read. */
- debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
+ debug_cond(DLEVEL >= 2, "%s:%d: end: failed\n",
__func__, __LINE__);
}
work_mid = (work_bgn + work_end) / 2;
- debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
+ debug_cond(DLEVEL >= 2, "work_bgn=%d work_end=%d work_mid=%d\n",
work_bgn, work_end, work_mid);
/* Get the middle delay to be less than a VFIFO delay */
tmp_delay = (iocfg->dqs_en_phase_max + 1) * iocfg->delay_per_opa_tap;
- debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
+ debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay);
work_mid %= tmp_delay;
- debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
+ debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid);
tmp_delay = rounddown(work_mid, iocfg->delay_per_opa_tap);
if (tmp_delay > iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap)
tmp_delay = iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap;
p = tmp_delay / iocfg->delay_per_opa_tap;
- debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
+ debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
- d = DIV_ROUND_UP(work_mid - tmp_delay, iocfg->delay_per_dqs_en_dchain_tap);
+ d = DIV_ROUND_UP(work_mid - tmp_delay,
+ iocfg->delay_per_dqs_en_dchain_tap);
if (d > iocfg->dqs_en_delay_max)
d = iocfg->dqs_en_delay_max;
tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap;
- debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
+ debug_cond(DLEVEL >= 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
* because the largest possible margin in 1 VFIFO cycle.
*/
for (i = 0; i < misccfg->read_valid_fifo_size; i++) {
- debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
+ debug_cond(DLEVEL >= 2, "find_dqs_en_phase: center\n");
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
0)) {
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d center: found: ptap=%u dtap=%u\n",
__func__, __LINE__, p, d);
return 0;
rw_mgr_incr_vfifo(grp);
}
- debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
+ debug_cond(DLEVEL >= 2, "%s:%d center: failed.\n",
__func__, __LINE__);
return -EINVAL;
}
u32 d, p, i;
u32 dtaps_per_ptap;
u32 work_bgn, work_end;
- u32 found_passing_read, found_failing_read, initial_failing_dtap;
+ u32 found_passing_read, found_failing_read = 0, initial_failing_dtap;
int ret;
debug("%s:%d %u\n", __func__, __LINE__, grp);
scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
/* Step 0: Determine number of delay taps for each phase tap. */
- dtaps_per_ptap = iocfg->delay_per_opa_tap / iocfg->delay_per_dqs_en_dchain_tap;
+ dtaps_per_ptap = iocfg->delay_per_opa_tap /
+ iocfg->delay_per_dqs_en_dchain_tap;
/* Step 1: First push vfifo until we get a failing read. */
find_vfifo_failing_read(grp);
d = 0;
- debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
+ debug_cond(DLEVEL >= 2, "%s:%d p: ptap=%u\n",
__func__, __LINE__, p);
}
if (d != 0)
work_end -= iocfg->delay_per_dqs_en_dchain_tap;
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d p/d: ptap=%u dtap=%u end=%u\n",
__func__, __LINE__, p, d - 1, work_end);
if (work_end < work_bgn) {
/* nil range */
- debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
+ debug_cond(DLEVEL >= 2, "%s:%d end-2: failed\n",
__func__, __LINE__);
return -EINVAL;
}
- debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
+ debug_cond(DLEVEL >= 2, "%s:%d found range [%u,%u]\n",
__func__, __LINE__, work_bgn, work_end);
/*
* To do that we'll back up a ptap and re-find the edge of the
* window using dtaps
*/
- debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
+ debug_cond(DLEVEL >= 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
__func__, __LINE__);
/* Special case code for backing up a phase */
if (p == 0) {
p = iocfg->dqs_en_phase_max;
rw_mgr_decr_vfifo(grp);
- debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
+ debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n",
__func__, __LINE__, p);
} else {
p = p - 1;
- debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
+ debug_cond(DLEVEL >= 2, "%s:%d backedup phase only: p=%u",
__func__, __LINE__, p);
}
*/
/* Find a passing read. */
- debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
+ debug_cond(DLEVEL >= 2, "%s:%d find passing read\n",
__func__, __LINE__);
initial_failing_dtap = d;
found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
if (found_passing_read) {
/* Find a failing read. */
- debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
+ debug_cond(DLEVEL >= 2, "%s:%d find failing read\n",
__func__, __LINE__);
d++;
found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
&d);
} else {
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
__func__, __LINE__);
}
dtaps_per_ptap = d - initial_failing_dtap;
writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
- debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
+ debug_cond(DLEVEL >= 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
__func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
/* Step 6: Find the centre of the window. */
}
*sticky_bit_chk = *sticky_bit_chk | *bit_chk;
ret = ret && (*sticky_bit_chk == correct_mask);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d center(left): dtap=%u => %u == %u && %u",
__func__, __LINE__, d,
*sticky_bit_chk, correct_mask, ret);
u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
- const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
- const u32 dqs_max = write ? iocfg->io_out1_delay_max : iocfg->dqs_in_delay_max;
+ const u32 delay_max = write ? iocfg->io_out1_delay_max :
+ iocfg->io_in_delay_max;
+ const u32 dqs_max = write ? iocfg->io_out1_delay_max :
+ iocfg->dqs_in_delay_max;
const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
rwcfg->mem_dq_per_read_dqs;
u32 stop, bit_chk;
*sticky_bit_chk = 0;
for (i = per_dqs - 1; i >= 0; i--) {
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
__func__, __LINE__, i, left_edge[i],
i, right_edge[i]);
if ((left_edge[i] == delay_max + 1) &&
(right_edge[i] != delay_max + 1)) {
right_edge[i] = delay_max + 1;
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d vfifo_center: reset right_edge[%u]: %d\n",
__func__, __LINE__, i, right_edge[i]);
}
*sticky_bit_chk |= 1;
}
}
-
-
}
/**
u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
- const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
- const u32 dqs_max = write ? iocfg->io_out1_delay_max : iocfg->dqs_in_delay_max;
+ const u32 delay_max = write ? iocfg->io_out1_delay_max :
+ iocfg->io_in_delay_max;
+ const u32 dqs_max = write ? iocfg->io_out1_delay_max :
+ iocfg->dqs_in_delay_max;
const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
rwcfg->mem_dq_per_read_dqs;
u32 stop, bit_chk;
} else { /* READ-ONLY */
scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
if (iocfg->shift_dqs_en_when_shift_dqs) {
- uint32_t delay = d + start_dqs_en;
+ u32 delay = d + start_dqs_en;
if (delay > iocfg->dqs_en_delay_max)
delay = iocfg->dqs_en_delay_max;
scc_mgr_set_dqs_en_delay(read_group, delay);
use_read_test);
if (stop == 1) {
if (write && (d == 0)) { /* WRITE-ONLY */
- for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
+ for (i = 0; i < rwcfg->mem_dq_per_write_dqs;
+ i++) {
/*
* d = 0 failed, but it passed when
* testing the left edge, so it must be
}
}
- debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ",
+ debug_cond(DLEVEL >= 2, "%s:%d center[r,d=%u]: ",
__func__, __LINE__, d);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"bit_chk_test=%i left_edge[%u]: %d ",
bit_chk & 1, i, left_edge[i]);
- debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
+ debug_cond(DLEVEL >= 2, "right_edge[%u]: %d\n", i,
right_edge[i]);
bit_chk >>= 1;
}
/* Check that all bits have a window */
for (i = 0; i < per_dqs; i++) {
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
__func__, __LINE__, i, left_edge[i],
i, right_edge[i]);
(*mid_min)++;
*mid_min = *mid_min / 2;
- debug_cond(DLEVEL == 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
+ debug_cond(DLEVEL >= 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
__func__, __LINE__, *mid_min, min_index);
return min_index;
}
const int min_index, const int test_bgn,
int *dq_margin, int *dqs_margin)
{
- const u32 delay_max = write ? iocfg->io_out1_delay_max : iocfg->io_in_delay_max;
- const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ const s32 delay_max = write ? iocfg->io_out1_delay_max :
+ iocfg->io_in_delay_max;
+ const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
rwcfg->mem_dq_per_read_dqs;
- const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
+ const s32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
SCC_MGR_IO_IN_DELAY_OFFSET;
- const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
+ const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
- u32 temp_dq_io_delay1, temp_dq_io_delay2;
+ s32 temp_dq_io_delay1;
int shift_dq, i, p;
/* Initialize data for export structures */
(left_edge[min_index] - right_edge[min_index]))/2 +
(orig_mid_min - mid_min);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"vfifo_center: before: shift_dq[%u]=%d\n",
i, shift_dq);
- temp_dq_io_delay1 = readl(addr + (p << 2));
- temp_dq_io_delay2 = readl(addr + (i << 2));
+ temp_dq_io_delay1 = readl(addr + (i << 2));
if (shift_dq + temp_dq_io_delay1 > delay_max)
- shift_dq = delay_max - temp_dq_io_delay2;
+ shift_dq = delay_max - temp_dq_io_delay1;
else if (shift_dq + temp_dq_io_delay1 < 0)
shift_dq = -temp_dq_io_delay1;
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"vfifo_center: after: shift_dq[%u]=%d\n",
i, shift_dq);
if (write)
- scc_mgr_set_dq_out1_delay(i, temp_dq_io_delay1 + shift_dq);
+ scc_mgr_set_dq_out1_delay(i,
+ temp_dq_io_delay1 + shift_dq);
else
- scc_mgr_set_dq_in_delay(p, temp_dq_io_delay1 + shift_dq);
+ scc_mgr_set_dq_in_delay(p,
+ temp_dq_io_delay1 + shift_dq);
scc_mgr_load_dq(p);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"vfifo_center: margin[%u]=[%d,%d]\n", i,
left_edge[i] - shift_dq + (-mid_min),
right_edge[i] + shift_dq - (-mid_min));
if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
*dqs_margin = right_edge[i] + shift_dq - (-mid_min);
}
-
}
/**
* Store these as signed since there are comparisons with
* signed numbers.
*/
- uint32_t sticky_bit_chk;
+ u32 sticky_bit_chk;
int32_t left_edge[rwcfg->mem_dq_per_read_dqs];
int32_t right_edge[rwcfg->mem_dq_per_read_dqs];
int32_t orig_mid_min, mid_min;
scc_mgr_load_dqs(rw_group);
writel(0, &sdr_scc_mgr->update);
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d vfifo_center: failed to find edge [%u]: %d %d",
__func__, __LINE__, i, left_edge[i], right_edge[i]);
if (use_read_test) {
new_dqs = 0;
mid_min = start_dqs - new_dqs;
- debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
+ debug_cond(DLEVEL >= 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
mid_min, new_dqs);
if (iocfg->shift_dqs_en_when_shift_dqs) {
if (start_dqs_en - mid_min > iocfg->dqs_en_delay_max)
- mid_min += start_dqs_en - mid_min - iocfg->dqs_en_delay_max;
+ mid_min += start_dqs_en - mid_min -
+ iocfg->dqs_en_delay_max;
else if (start_dqs_en - mid_min < 0)
mid_min += start_dqs_en - mid_min;
}
new_dqs = start_dqs - mid_min;
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
start_dqs,
iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1,
/* Move DQS */
scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
scc_mgr_load_dqs(rw_group);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
__func__, __LINE__, dq_margin, dqs_margin);
/* Set a particular DQ/DQS phase. */
scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
- debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
+ debug_cond(DLEVEL >= 1, "%s:%d guaranteed write: g=%u p=%u\n",
__func__, __LINE__, rw_group, phase);
/*
*/
ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
if (ret)
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d Guaranteed read test failed: g=%u p=%u\n",
__func__, __LINE__, rw_group, phase);
return ret;
for (i = 0, p = test_bgn, d = 0;
i < rwcfg->mem_dq_per_read_dqs;
i++, p++, d += delay_step) {
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
__func__, __LINE__, rw_group, r, i, p, d);
*/
ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
__func__, __LINE__, rw_group, !ret);
*/
static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
{
- uint32_t p, d;
- uint32_t dtaps_per_ptap;
- uint32_t failed_substage;
+ u32 p, d;
+ u32 dtaps_per_ptap;
+ u32 failed_substage;
int ret;
* detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
* Calibrate LFIFO to find smallest read latency.
*/
-static uint32_t rw_mgr_mem_calibrate_lfifo(void)
+static u32 rw_mgr_mem_calibrate_lfifo(void)
{
int found_one = 0;
do {
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
- debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
+ debug_cond(DLEVEL >= 2, "%s:%d lfifo: read_lat=%u",
__func__, __LINE__, gbl->curr_read_lat);
if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS,
/* Add a fudge factor to the read latency that was determined */
gbl->curr_read_lat += 2;
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d lfifo: success: using read_lat=%u\n",
__func__, __LINE__, gbl->curr_read_lat);
} else {
set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
CAL_SUBSTAGE_READ_LATENCY);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d lfifo: failed at initial read_lat=%u\n",
__func__, __LINE__, gbl->curr_read_lat);
}
/* For DQS, we go from 0...max */
d = max - di;
/*
- * Note: This only shifts DQS, so are we limiting ourselve to
- * width of DQ unnecessarily.
+ * Note: This only shifts DQS, so are we limiting
+ * ourselves to width of DQ unnecessarily.
*/
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + new_dqs);
orig_mid_min = mid_min;
new_dqs = start_dqs;
mid_min = 0;
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
__func__, __LINE__, start_dqs, new_dqs, mid_min);
writel(0, &sdr_scc_mgr->update);
/* Centre DM */
- debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
+ debug_cond(DLEVEL >= 2, "%s:%d write_center: DM\n", __func__, __LINE__);
/*
* Set the left and right edge of each bit to an illegal value.
left_edge[0] = -1 * bgn_best;
right_edge[0] = end_best;
- debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n",
+ debug_cond(DLEVEL >= 2, "%s:%d dm_calib: left=%d right=%d\n",
__func__, __LINE__, left_edge[0], right_edge[0]);
/* Move DQS (back to orig). */
scc_mgr_apply_group_dm_out1_delay(mid);
writel(0, &sdr_scc_mgr->update);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
__func__, __LINE__, left_edge[0], right_edge[0],
mid, dm_margin);
/* Export values. */
gbl->fom_out += dq_margin + dqs_margin;
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
__func__, __LINE__, dq_margin, dqs_margin, dm_margin);
writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
writel(rwcfg->activate_0_and_1_wait1,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
writel(rwcfg->activate_0_and_1_wait2,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* Activate rows. */
writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
*/
static void mem_skip_calibrate(void)
{
- uint32_t vfifo_offset;
- uint32_t i, j, r;
+ u32 vfifo_offset;
+ u32 i, j, r;
debug("%s:%d\n", __func__, __LINE__);
/* Need to update every shadow register set used by the interface */
*
* Hence, to make DQS aligned to CK, we need to delay
* DQS by:
- * (720 - 90 - 180 - 2 * (360 / iocfg->dll_chain_length))
+ * (720 - 90 - 180 - 2) *
+ * (360 / iocfg->dll_chain_length)
*
* Dividing the above by (360 / iocfg->dll_chain_length)
* gives us the number of ptaps, which simplies to:
* (1.25 * iocfg->dll_chain_length - 2)
*/
scc_mgr_set_dqdqs_output_phase(i,
- 1.25 * iocfg->dll_chain_length - 2);
+ ((125 * iocfg->dll_chain_length) / 100) - 2);
}
writel(0xff, &sdr_scc_mgr->dqs_ena);
writel(0xff, &sdr_scc_mgr->dqs_io_ena);
*
* Perform memory calibration.
*/
-static uint32_t mem_calibrate(void)
+static u32 mem_calibrate(void)
{
- uint32_t i;
- uint32_t rank_bgn, sr;
- uint32_t write_group, write_test_bgn;
- uint32_t read_group, read_test_bgn;
- uint32_t run_groups, current_run;
- uint32_t failing_groups = 0;
- uint32_t group_failed = 0;
+ u32 i;
+ u32 rank_bgn, sr;
+ u32 write_group, write_test_bgn;
+ u32 read_group, read_test_bgn;
+ u32 run_groups, current_run;
+ u32 failing_groups = 0;
+ u32 group_failed = 0;
const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width /
rwcfg->mem_if_write_dqs_width;
for (write_group = 0, write_test_bgn = 0; write_group
< rwcfg->mem_if_write_dqs_width; write_group++,
write_test_bgn += rwcfg->mem_dq_per_write_dqs) {
-
/* Initialize the group failure */
group_failed = 0;
read_test_bgn))
continue;
- if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ if (!(gbl->phy_debug_mode_flags &
+ PHY_DEBUG_SWEEP_ALL_GROUPS))
return 0;
/* The group failed, we're done. */
continue;
/* Not needed in quick mode! */
- if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
+ if (STATIC_CALIB_STEPS &
+ CALIB_SKIP_DELAY_SWEEPS)
continue;
/* Calibrate WRITEs */
if (!rw_mgr_mem_calibrate_writes(rank_bgn,
- write_group, write_test_bgn))
+ write_group,
+ write_test_bgn))
continue;
group_failed = 1;
- if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ if (!(gbl->phy_debug_mode_flags &
+ PHY_DEBUG_SWEEP_ALL_GROUPS))
return 0;
}
continue;
if (!rw_mgr_mem_calibrate_vfifo_end(read_group,
- read_test_bgn))
+ read_test_bgn))
continue;
- if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ if (!(gbl->phy_debug_mode_flags &
+ PHY_DEBUG_SWEEP_ALL_GROUPS))
return 0;
/* The group failed, we're done. */
static int run_mem_calibrate(void)
{
int pass;
+ u32 ctrl_cfg;
debug("%s:%d\n", __func__, __LINE__);
writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
/* Stop tracking manager. */
- clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
+ ctrl_cfg = readl(&sdr_ctrl->ctrl_cfg);
+ writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
+ &sdr_ctrl->ctrl_cfg);
phy_mgr_initialize();
rw_mgr_mem_initialize();
writel(0x2, &phy_mgr_cfg->mux_sel);
/* Start tracking manager. */
- setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
+ writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
return pass;
}
*/
static void debug_mem_calibrate(int pass)
{
- uint32_t debug_info;
+ u32 debug_info;
if (pass) {
- printf("%s: CALIBRATION PASSED\n", __FILE__);
+ debug("%s: CALIBRATION PASSED\n", __FILE__);
gbl->fom_in /= 2;
gbl->fom_out /= 2;
writel(debug_info, &phy_mgr_cfg->cal_debug_info);
writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
} else {
- printf("%s: CALIBRATION FAILED\n", __FILE__);
+ debug("%s: CALIBRATION FAILED\n", __FILE__);
debug_info = gbl->error_stage;
debug_info |= gbl->error_substage << 8;
writel(debug_info, &sdr_reg_file->failing_stage);
}
- printf("%s: Calibration complete\n", __FILE__);
+ debug("%s: Calibration complete\n", __FILE__);
}
/**
*/
static void initialize_hps_phy(void)
{
- uint32_t reg;
+ u32 reg;
/*
* Tracking also gets configured here because it's in the
* same register.
*/
- uint32_t trk_sample_count = 7500;
- uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
+ u32 trk_sample_count = 7500;
+ u32 trk_long_idle_sample_count = (10 << 16) | 100;
/*
* Format is number of outer loops in the 16 MSB, sample
* count in 16 LSB.
* Compute usable version of value in case we skip full
* computation later.
*/
- writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap) - 1,
+ writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap,
+ iocfg->delay_per_dchain_tap) - 1,
&sdr_reg_file->dtaps_per_ptap);
/* trk_sample_count */
{
struct param_type my_param;
struct gbl_type my_gbl;
- uint32_t pass;
+ u32 pass;
memset(&my_param, 0, sizeof(my_param));
memset(&my_gbl, 0, sizeof(my_gbl));
initialize_tracking();
- printf("%s: Preparing to start memory calibration\n", __FILE__);
+ debug("%s: Preparing to start memory calibration\n", __FILE__);
debug("%s:%d\n", __func__, __LINE__);
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm,
rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs,
rwcfg->mem_virtual_groups_per_read_dqs,
rwcfg->mem_virtual_groups_per_write_dqs);
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width,
rwcfg->mem_data_width, rwcfg->mem_data_mask_width,
iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap);
- debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
+ debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u",
iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length);
- debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
+ debug_cond(DLEVEL >= 1,
+ "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max,
iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max);
- debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
+ debug_cond(DLEVEL >= 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
iocfg->io_in_delay_max, iocfg->io_out1_delay_max,
iocfg->io_out2_delay_max);
- debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
+ debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
iocfg->dqs_in_reserve, iocfg->dqs_out_reserve);
hc_initialize_rom_data();
projects / oweals / u-boot.git / blobdiff