#include "sequencer_auto_inst_init.h"
#include "sequencer_defines.h"
-static void scc_mgr_load_dqs_for_write_group(uint32_t write_group);
-
static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
(struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
static struct socfpga_data_mgr *data_mgr =
(struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
+static struct socfpga_sdr_ctrl *sdr_ctrl =
+ (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+
#define DELTA_D 1
/*
}
}
-static void reg_file_set_group(uint32_t set_group)
+static void reg_file_set_group(u16 set_group)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(addr);
-
- /* Clear the group */
- cur_stage_group &= 0x0000FFFF;
-
- /* Set the group */
- cur_stage_group |= (set_group << 16);
-
- /* Write the data back */
- writel(cur_stage_group, addr);
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
}
-static void reg_file_set_stage(uint32_t set_stage)
+static void reg_file_set_stage(u8 set_stage)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(addr);
-
- /* Clear the stage and substage */
- cur_stage_group &= 0xFFFF0000;
-
- /* Set the stage */
- cur_stage_group |= (set_stage & 0x000000FF);
-
- /* Write the data back */
- writel(cur_stage_group, addr);
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
}
-static void reg_file_set_sub_stage(uint32_t set_sub_stage)
+static void reg_file_set_sub_stage(u8 set_sub_stage)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(addr);
-
- /* Clear the substage */
- cur_stage_group &= 0xFFFF00FF;
-
- /* Set the sub stage */
- cur_stage_group |= ((set_sub_stage << 8) & 0x0000FF00);
-
- /* Write the data back */
- writel(cur_stage_group, addr);
+ set_sub_stage &= 0xff;
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
}
static void initialize(void)
{
- u32 addr = (u32)&phy_mgr_cfg->mux_sel;
-
debug("%s:%d\n", __func__, __LINE__);
/* USER calibration has control over path to memory */
/*
* 0: AFI Mux Select
* 1: DDIO Mux Select
*/
- writel(0x3, addr);
+ writel(0x3, &phy_mgr_cfg->mux_sel);
/* USER memory clock is not stable we begin initialization */
- addr = (u32)&phy_mgr_cfg->reset_mem_stbl;
- writel(0, addr);
+ writel(0, &phy_mgr_cfg->reset_mem_stbl);
/* USER calibration status all set to zero */
- addr = (u32)&phy_mgr_cfg->cal_status;
- writel(0, addr);
+ writel(0, &phy_mgr_cfg->cal_status);
- addr = (u32)&phy_mgr_cfg->cal_debug_info;
- writel(0, addr);
+ writel(0, &phy_mgr_cfg->cal_debug_info);
if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
param->read_correct_mask_vg = ((uint32_t)1 <<
uint32_t odt_mask_0 = 0;
uint32_t odt_mask_1 = 0;
uint32_t cs_and_odt_mask;
- uint32_t addr;
if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
(0xFF & ~(1 << rank)) |
((0xFF & odt_mask_0) << 8) |
((0xFF & odt_mask_1) << 16);
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_SET_CS_AND_ODT_MASK_OFFSET;
- writel(cs_and_odt_mask, addr);
+ writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
}
-static void scc_mgr_initialize(void)
+/**
+ * scc_mgr_set() - Set SCC Manager register
+ * @off: Base offset in SCC Manager space
+ * @grp: Read/Write group
+ * @val: Value to be set
+ *
+ * This function sets the SCC Manager (Scan Chain Control Manager) register.
+ */
+static void scc_mgr_set(u32 off, u32 grp, u32 val)
{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_RFILE_OFFSET;
+ writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
+}
+/**
+ * scc_mgr_initialize() - Initialize SCC Manager registers
+ *
+ * Initialize SCC Manager registers.
+ */
+static void scc_mgr_initialize(void)
+{
/*
- * Clear register file for HPS
- * 16 (2^4) is the size of the full register file in the scc mgr:
- * RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
- * MEM_IF_READ_DQS_WIDTH - 1) + 1;
+ * Clear register file for HPS. 16 (2^4) is the size of the
+ * full register file in the scc mgr:
+ * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
+ * MEM_IF_READ_DQS_WIDTH - 1);
*/
- uint32_t i;
+ int i;
+
for (i = 0; i < 16; i++) {
debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
__func__, __LINE__, i);
- writel(0, addr + (i << 2));
+ scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
}
}
-static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,
- uint32_t delay)
+static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
+ scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
+}
- /* Load the setting in the SCC manager */
- writel(delay, addr + (read_group << 2));
+static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
+{
+ scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
}
-static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group,
- uint32_t delay)
+static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
+ scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
+}
- writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
+{
+ scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
}
-static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
+static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_PHASE_OFFSET;
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ delay);
+}
- /* Load the setting in the SCC manager */
- writel(phase, addr + (read_group << 2));
+static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
+{
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
}
-static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
- uint32_t phase)
+static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
{
- uint32_t r;
- uint32_t update_scan_chains;
- uint32_t addr;
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
+}
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- /*
- * USER although the h/w doesn't support different phases per
- * shadow register, for simplicity our scc manager modeling
- * keeps different phase settings per shadow reg, and it's
- * important for us to keep them in sync to match h/w.
- * for efficiency, the scan chain update should occur only
- * once to sr0.
- */
- update_scan_chains = (r == 0) ? 1 : 0;
+static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
+{
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ delay);
+}
- scc_mgr_set_dqs_en_phase(read_group, phase);
+static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
+{
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
+ RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
+ delay);
+}
- if (update_scan_chains) {
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(read_group, addr);
+/* load up dqs config settings */
+static void scc_mgr_load_dqs(uint32_t dqs)
+{
+ writel(dqs, &sdr_scc_mgr->dqs_ena);
+}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
- }
- }
+/* load up dqs io config settings */
+static void scc_mgr_load_dqs_io(void)
+{
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
}
-static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group,
- uint32_t phase)
+/* load up dq config settings */
+static void scc_mgr_load_dq(uint32_t dq_in_group)
{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQDQS_OUT_PHASE_OFFSET;
+ writel(dq_in_group, &sdr_scc_mgr->dq_ena);
+}
- /* Load the setting in the SCC manager */
- writel(phase, addr + (write_group << 2));
+/* load up dm config settings */
+static void scc_mgr_load_dm(uint32_t dm)
+{
+ writel(dm, &sdr_scc_mgr->dm_ena);
}
-static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
- uint32_t phase)
+/**
+ * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
+ * @off: Base offset in SCC Manager space
+ * @grp: Read/Write group
+ * @val: Value to be set
+ * @update: If non-zero, trigger SCC Manager update for all ranks
+ *
+ * This function sets the SCC Manager (Scan Chain Control Manager) register
+ * and optionally triggers the SCC update for all ranks.
+ */
+static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
+ const int update)
{
- uint32_t r;
- uint32_t update_scan_chains;
- uint32_t addr;
+ u32 r;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
- /*
- * USER although the h/w doesn't support different phases per
- * shadow register, for simplicity our scc manager modeling
- * keeps different phase settings per shadow reg, and it's
- * important for us to keep them in sync to match h/w.
- * for efficiency, the scan chain update should occur only
- * once to sr0.
- */
- update_scan_chains = (r == 0) ? 1 : 0;
+ scc_mgr_set(off, grp, val);
- scc_mgr_set_dqdqs_output_phase(write_group, phase);
-
- if (update_scan_chains) {
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(write_group, addr);
-
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ if (update || (r == 0)) {
+ writel(grp, &sdr_scc_mgr->dqs_ena);
+ writel(0, &sdr_scc_mgr->update);
}
}
}
-static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
+static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_DELAY_OFFSET;
+ /*
+ * USER although the h/w doesn't support different phases per
+ * shadow register, for simplicity our scc manager modeling
+ * keeps different phase settings per shadow reg, and it's
+ * important for us to keep them in sync to match h/w.
+ * for efficiency, the scan chain update should occur only
+ * once to sr0.
+ */
+ scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
+ read_group, phase, 0);
+}
- /* Load the setting in the SCC manager */
- writel(delay + IO_DQS_EN_DELAY_OFFSET, addr +
- (read_group << 2));
+static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
+ uint32_t phase)
+{
+ /*
+ * USER although the h/w doesn't support different phases per
+ * shadow register, for simplicity our scc manager modeling
+ * keeps different phase settings per shadow reg, and it's
+ * important for us to keep them in sync to match h/w.
+ * for efficiency, the scan chain update should occur only
+ * once to sr0.
+ */
+ scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
+ write_group, phase, 0);
}
static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
uint32_t delay)
{
- uint32_t r;
- uint32_t addr;
-
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- scc_mgr_set_dqs_en_delay(read_group, delay);
-
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(read_group, addr);
- /*
- * In shadow register mode, the T11 settings are stored in
- * registers in the core, which are updated by the DQS_ENA
- * signals. Not issuing the SCC_MGR_UPD command allows us to
- * save lots of rank switching overhead, by calling
- * select_shadow_regs_for_update with update_scan_chains
- * set to 0.
- */
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
- }
/*
* In shadow register mode, the T11 settings are stored in
* registers in the core, which are updated by the DQS_ENA
* select_shadow_regs_for_update with update_scan_chains
* set to 0.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
+ read_group, delay, 1);
+ writel(0, &sdr_scc_mgr->update);
}
-static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
+/**
+ * scc_mgr_set_oct_out1_delay() - Set OCT output delay
+ * @write_group: Write group
+ * @delay: Delay value
+ *
+ * This function sets the OCT output delay in SCC manager.
+ */
+static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
{
- uint32_t read_group;
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_OCT_OUT1_DELAY_OFFSET;
-
+ const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const int base = write_group * ratio;
+ int i;
/*
* Load the setting in the SCC manager
* Although OCT affects only write data, the OCT delay is controlled
* For protocols where a write group consists of multiple read groups,
* the setting must be set multiple times.
*/
- for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
- read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
- writel(delay, addr + (read_group << 2));
-}
-
-static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
- uint32_t dq_in_group, uint32_t delay)
-{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr + (dq_in_group << 2));
-}
-
-static void scc_mgr_set_dq_in_delay(uint32_t write_group,
- uint32_t dq_in_group, uint32_t delay)
-{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr + (dq_in_group << 2));
+ for (i = 0; i < ratio; i++)
+ scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
}
+/**
+ * scc_mgr_set_hhp_extras() - Set HHP extras.
+ *
+ * Load the fixed setting in the SCC manager HHP extras.
+ */
static void scc_mgr_set_hhp_extras(void)
{
/*
* Load the fixed setting in the SCC manager
- * bits: 0:0 = 1'b1 - dqs bypass
- * bits: 1:1 = 1'b1 - dq bypass
- * bits: 4:2 = 3'b001 - rfifo_mode
- * bits: 6:5 = 2'b01 - rfifo clock_select
- * bits: 7:7 = 1'b0 - separate gating from ungating setting
- * bits: 8:8 = 1'b0 - separate OE from Output delay setting
+ * bits: 0:0 = 1'b1 - DQS bypass
+ * bits: 1:1 = 1'b1 - DQ bypass
+ * bits: 4:2 = 3'b001 - rfifo_mode
+ * bits: 6:5 = 2'b01 - rfifo clock_select
+ * bits: 7:7 = 1'b0 - separate gating from ungating setting
+ * bits: 8:8 = 1'b0 - separate OE from Output delay setting
*/
- uint32_t value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0);
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_GLOBALS_OFFSET;
-
- writel(value, addr + SCC_MGR_HHP_EXTRAS_OFFSET);
-}
-
-static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
- uint32_t delay)
-{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
+ const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
+ (1 << 2) | (1 << 1) | (1 << 0);
+ const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_HHP_GLOBALS_OFFSET |
+ SCC_MGR_HHP_EXTRAS_OFFSET;
- /* Load the setting in the SCC manager */
- writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
-}
-
-static void scc_mgr_set_dm_out1_delay(uint32_t write_group,
- uint32_t dm, uint32_t delay)
-{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr +
- ((RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm) << 2));
+ debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
+ __func__, __LINE__);
+ writel(value, addr);
+ debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
+ __func__, __LINE__);
}
-/*
- * USER Zero all DQS config
- * TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
+/**
+ * scc_mgr_zero_all() - Zero all DQS config
+ *
+ * Zero all DQS config.
*/
static void scc_mgr_zero_all(void)
{
- uint32_t i, r;
- uint32_t addr;
+ int i, r;
/*
* USER Zero all DQS config settings, across all groups and all
* shadow registers
*/
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
- NUM_RANKS_PER_SHADOW_REG) {
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
/*
* The phases actually don't exist on a per-rank basis,
for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
scc_mgr_set_dqdqs_output_phase(i, 0);
- /* av/cv don't have out2 */
+ /* Arria V/Cyclone V don't have out2. */
scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
}
}
- /* multicast to all DQS group enables */
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(0xff, addr);
-
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ /* Multicast to all DQS group enables. */
+ writel(0xff, &sdr_scc_mgr->dqs_ena);
+ writel(0, &sdr_scc_mgr->update);
}
-static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
+/**
+ * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
+ * @write_group: Write group
+ *
+ * Set bypass mode and trigger SCC update.
+ */
+static void scc_set_bypass_mode(const u32 write_group)
{
- uint32_t addr;
- /* mode = 0 : Do NOT bypass - Half Rate Mode */
- /* mode = 1 : Bypass - Full Rate Mode */
+ /* Multicast to all DQ enables. */
+ writel(0xff, &sdr_scc_mgr->dq_ena);
+ writel(0xff, &sdr_scc_mgr->dm_ena);
- /* only need to set once for all groups, pins, dq, dqs, dm */
- if (write_group == 0) {
- debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", __func__,
- __LINE__);
- scc_mgr_set_hhp_extras();
- debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
- __func__, __LINE__);
- }
- /* multicast to all DQ enables */
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, addr);
-
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, addr);
+ /* Update current DQS IO enable. */
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
- /* update current DQS IO enable */
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0, addr);
+ /* Update the DQS logic. */
+ writel(write_group, &sdr_scc_mgr->dqs_ena);
- /* update the DQS logic */
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(write_group, addr);
+ /* Hit update. */
+ writel(0, &sdr_scc_mgr->update);
+}
- /* hit update */
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+/**
+ * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
+ * @write_group: Write group
+ *
+ * Load DQS settings for Write Group, do not trigger SCC update.
+ */
+static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
+{
+ const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const int base = write_group * ratio;
+ int i;
+ /*
+ * Load the setting in the SCC manager
+ * Although OCT affects only write data, the OCT delay is controlled
+ * by the DQS logic block which is instantiated once per read group.
+ * For protocols where a write group consists of multiple read groups,
+ * the setting must be set multiple times.
+ */
+ for (i = 0; i < ratio; i++)
+ writel(base + i, &sdr_scc_mgr->dqs_ena);
}
-static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
- int32_t out_only)
+/**
+ * scc_mgr_zero_group() - Zero all configs for a group
+ *
+ * Zero DQ, DM, DQS and OCT configs for a group.
+ */
+static void scc_mgr_zero_group(const u32 write_group, const int out_only)
{
- uint32_t i, r;
- uint32_t addr;
+ int i, r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
- NUM_RANKS_PER_SHADOW_REG) {
- /* Zero all DQ config settings */
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ /* Zero all DQ config settings. */
for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
- scc_mgr_set_dq_out1_delay(write_group, i, 0);
+ scc_mgr_set_dq_out1_delay(i, 0);
if (!out_only)
- scc_mgr_set_dq_in_delay(write_group, i, 0);
+ scc_mgr_set_dq_in_delay(i, 0);
}
- /* multicast to all DQ enables */
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, addr);
+ /* Multicast to all DQ enables. */
+ writel(0xff, &sdr_scc_mgr->dq_ena);
- /* Zero all DM config settings */
- for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
- scc_mgr_set_dm_out1_delay(write_group, i, 0);
- }
+ /* Zero all DM config settings. */
+ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
+ scc_mgr_set_dm_out1_delay(i, 0);
- /* multicast to all DM enables */
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, addr);
+ /* Multicast to all DM enables. */
+ writel(0xff, &sdr_scc_mgr->dm_ena);
- /* zero all DQS io settings */
+ /* Zero all DQS IO settings. */
if (!out_only)
- scc_mgr_set_dqs_io_in_delay(write_group, 0);
- /* av/cv don't have out2 */
- scc_mgr_set_dqs_out1_delay(write_group, IO_DQS_OUT_RESERVE);
+ scc_mgr_set_dqs_io_in_delay(0);
+
+ /* Arria V/Cyclone V don't have out2. */
+ scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
scc_mgr_load_dqs_for_write_group(write_group);
- /* multicast to all DQS IO enables (only 1) */
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0, addr);
+ /* Multicast to all DQS IO enables (only 1 in total). */
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
- /* hit update to zero everything */
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ /* Hit update to zero everything. */
+ writel(0, &sdr_scc_mgr->update);
}
}
-/* load up dqs config settings */
-static void scc_mgr_load_dqs(uint32_t dqs)
-{
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
-
- writel(dqs, addr);
-}
-
-static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
-{
- uint32_t read_group;
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
- /*
- * Although OCT affects only write data, the OCT delay is controlled
- * by the DQS logic block which is instantiated once per read group.
- * For protocols where a write group consists of multiple read groups,
- * the setting must be scanned multiple times.
- */
- for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
- read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
- writel(read_group, addr);
-}
-
-/* load up dqs io config settings */
-static void scc_mgr_load_dqs_io(void)
-{
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_io_ena;
-
- writel(0, addr);
-}
-
-/* load up dq config settings */
-static void scc_mgr_load_dq(uint32_t dq_in_group)
-{
- uint32_t addr = (u32)&sdr_scc_mgr->dq_ena;
-
- writel(dq_in_group, addr);
-}
-
-/* load up dm config settings */
-static void scc_mgr_load_dm(uint32_t dm)
-{
- uint32_t addr = (u32)&sdr_scc_mgr->dm_ena;
-
- writel(dm, addr);
-}
-
/*
* apply and load a particular input delay for the DQ pins in a group
* group_bgn is the index of the first dq pin (in the write group)
*/
-static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group,
- uint32_t group_bgn, uint32_t delay)
+static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
{
uint32_t i, p;
for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
- scc_mgr_set_dq_in_delay(write_group, p, delay);
+ scc_mgr_set_dq_in_delay(p, delay);
scc_mgr_load_dq(p);
}
}
-/* apply and load a particular output delay for the DQ pins in a group */
-static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group,
- uint32_t group_bgn,
- uint32_t delay1)
+/**
+ * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
+ * @delay: Delay value
+ *
+ * Apply and load a particular output delay for the DQ pins in a group.
+ */
+static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
{
- uint32_t i, p;
+ int i;
- for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
- scc_mgr_set_dq_out1_delay(write_group, i, delay1);
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ scc_mgr_set_dq_out1_delay(i, delay);
scc_mgr_load_dq(i);
}
}
/* apply and load a particular output delay for the DM pins in a group */
-static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group,
- uint32_t delay1)
+static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
{
uint32_t i;
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
- scc_mgr_set_dm_out1_delay(write_group, i, delay1);
+ scc_mgr_set_dm_out1_delay(i, delay1);
scc_mgr_load_dm(i);
}
}
static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
uint32_t delay)
{
- scc_mgr_set_dqs_out1_delay(write_group, delay);
+ scc_mgr_set_dqs_out1_delay(delay);
scc_mgr_load_dqs_io();
scc_mgr_set_oct_out1_delay(write_group, delay);
scc_mgr_load_dqs_for_write_group(write_group);
}
-/* apply a delay to the entire output side: DQ, DM, DQS, OCT */
-static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group,
- uint32_t group_bgn,
- uint32_t delay)
+/**
+ * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
+ * @write_group: Write group
+ * @delay: Delay value
+ *
+ * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
+ */
+static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
+ const u32 delay)
{
- uint32_t i, p, new_delay;
-
- /* dq shift */
- for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
- new_delay = READ_SCC_DQ_OUT2_DELAY;
- new_delay += delay;
-
- if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQ[%u,%u]:\
- %u > %lu => %lu", __func__, __LINE__,
- write_group, group_bgn, delay, i, p, new_delay,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
- }
+ u32 i, new_delay;
+ /* DQ shift */
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
scc_mgr_load_dq(i);
- }
-
- /* dm shift */
- for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
- new_delay = READ_SCC_DM_IO_OUT2_DELAY;
- new_delay += delay;
-
- if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DM[%u]:\
- %u > %lu => %lu\n", __func__, __LINE__,
- write_group, group_bgn, delay, i, new_delay,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
- }
+ /* DM shift */
+ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
scc_mgr_load_dm(i);
- }
-
- /* dqs shift */
- new_delay = READ_SCC_DQS_IO_OUT2_DELAY;
- new_delay += delay;
+ /* DQS shift */
+ new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
- " adding %u to OUT1\n", __func__, __LINE__,
- write_group, group_bgn, delay, new_delay,
- IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
+ debug_cond(DLEVEL == 1,
+ "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
+ __func__, __LINE__, write_group, delay, new_delay,
+ IO_IO_OUT2_DELAY_MAX,
new_delay - IO_IO_OUT2_DELAY_MAX);
- scc_mgr_set_dqs_out1_delay(write_group, new_delay -
- IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
+ new_delay -= IO_IO_OUT2_DELAY_MAX;
+ scc_mgr_set_dqs_out1_delay(new_delay);
}
scc_mgr_load_dqs_io();
- /* oct shift */
- new_delay = READ_SCC_OCT_OUT2_DELAY;
- new_delay += delay;
-
+ /* OCT shift */
+ new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
- " adding %u to OUT1\n", __func__, __LINE__,
- write_group, group_bgn, delay, new_delay,
- IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
+ debug_cond(DLEVEL == 1,
+ "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
+ __func__, __LINE__, write_group, delay,
+ new_delay, IO_IO_OUT2_DELAY_MAX,
new_delay - IO_IO_OUT2_DELAY_MAX);
- scc_mgr_set_oct_out1_delay(write_group, new_delay -
- IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
+ new_delay -= IO_IO_OUT2_DELAY_MAX;
+ scc_mgr_set_oct_out1_delay(write_group, new_delay);
}
scc_mgr_load_dqs_for_write_group(write_group);
}
-/*
- * USER apply a delay to the entire output side (DQ, DM, DQS, OCT)
- * and to all ranks
+/**
+ * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
+ * @write_group: Write group
+ * @delay: Delay value
+ *
+ * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
*/
-static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
- uint32_t write_group, uint32_t group_bgn, uint32_t delay)
+static void
+scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
+ const u32 delay)
{
- uint32_t r;
- uint32_t addr = (u32)&sdr_scc_mgr->update;
+ int r;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- scc_mgr_apply_group_all_out_delay_add(write_group,
- group_bgn, delay);
- writel(0, addr);
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ scc_mgr_apply_group_all_out_delay_add(write_group, delay);
+ writel(0, &sdr_scc_mgr->update);
}
}
-/* optimization used to recover some slots in ddr3 inst_rom */
-/* could be applied to other protocols if we wanted to */
+/**
+ * set_jump_as_return() - Return instruction optimization
+ *
+ * Optimization used to recover some slots in ddr3 inst_rom could be
+ * applied to other protocols if we wanted to
+ */
static void set_jump_as_return(void)
{
- uint32_t addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
-
/*
- * to save space, we replace return with jump to special shared
+ * To save space, we replace return with jump to special shared
* RETURN instruction so we set the counter to large value so that
- * we always jump
+ * we always jump.
*/
- writel(0xff, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_RETURN, addr);
+ writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
}
/*
uint8_t inner = 0;
uint8_t outer = 0;
uint16_t c_loop = 0;
- uint32_t addr;
debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
* overhead
*/
if (afi_clocks <= 0x100) {
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
+ &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_IDLE_LOOP1, addr);
+ writel(RW_MGR_IDLE_LOOP1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_IDLE_LOOP1, addr);
+ writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
+ &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
+ &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_IDLE_LOOP2, addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_IDLE_LOOP2, addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* hack to get around compiler not being smart enough */
if (afi_clocks <= 0x10000) {
/* only need to run once */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_IDLE_LOOP2, addr);
+ writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
do {
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_IDLE_LOOP2, addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} while (c_loop-- != 0);
}
}
debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
}
-static void rw_mgr_mem_initialize(void)
+/**
+ * rw_mgr_mem_init_load_regs() - Load instruction registers
+ * @cntr0: Counter 0 value
+ * @cntr1: Counter 1 value
+ * @cntr2: Counter 2 value
+ * @jump: Jump instruction value
+ *
+ * Load instruction registers.
+ */
+static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
{
- uint32_t r;
- uint32_t addr;
+ uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+
+ /* Load counters */
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
+ &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
+ &sdr_rw_load_mgr_regs->load_cntr1);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
+ &sdr_rw_load_mgr_regs->load_cntr2);
+
+ /* Load jump address */
+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+
+ /* Execute count instruction */
+ writel(jump, grpaddr);
+}
+
+/**
+ * rw_mgr_mem_load_user() - Load user calibration values
+ * @fin1: Final instruction 1
+ * @fin2: Final instruction 2
+ * @precharge: If 1, precharge the banks at the end
+ *
+ * Load user calibration values and optionally precharge the banks.
+ */
+static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
+ const int precharge)
+{
+ u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ u32 r;
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
+ if (param->skip_ranks[r]) {
+ /* request to skip the rank */
+ continue;
+ }
+
+ /* set rank */
+ set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
+
+ /* precharge all banks ... */
+ if (precharge)
+ writel(RW_MGR_PRECHARGE_ALL, grpaddr);
+
+ /*
+ * USER Use Mirror-ed commands for odd ranks if address
+ * mirrorring is on
+ */
+ if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
+ set_jump_as_return();
+ writel(RW_MGR_MRS2_MIRR, grpaddr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS3_MIRR, grpaddr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS1_MIRR, grpaddr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(fin1, grpaddr);
+ } else {
+ set_jump_as_return();
+ writel(RW_MGR_MRS2, grpaddr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS3, grpaddr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS1, grpaddr);
+ set_jump_as_return();
+ writel(fin2, grpaddr);
+ }
+ if (precharge)
+ continue;
+
+ set_jump_as_return();
+ writel(RW_MGR_ZQCL, grpaddr);
+
+ /* tZQinit = tDLLK = 512 ck cycles */
+ delay_for_n_mem_clocks(512);
+ }
+}
+
+static void rw_mgr_mem_initialize(void)
+{
debug("%s:%d\n", __func__, __LINE__);
/* The reset / cke part of initialization is broadcasted to all ranks */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_SET_CS_AND_ODT_MASK_OFFSET;
- writel(RW_MGR_RANK_ALL, addr);
+ writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
/*
* Here's how you load register for a loop
* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
* b = 6A
*/
-
- /* Load counters */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
- addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
- addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
- addr);
-
- /* Load jump address */
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
-
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
-
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
-
- /* Execute count instruction */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
+ rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
+ SEQ_TINIT_CNTR2_VAL,
+ RW_MGR_INIT_RESET_0_CKE_0);
/* indicate that memory is stable */
- addr = (u32)&phy_mgr_cfg->reset_mem_stbl;
- writel(1, addr);
+ writel(1, &phy_mgr_cfg->reset_mem_stbl);
/*
* transition the RESET to high
* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
* b = FF
*/
-
- /* Load counters */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
- addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
- addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
- addr);
-
- /* Load jump address */
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
-
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
+ rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
+ SEQ_TRESET_CNTR2_VAL,
+ RW_MGR_INIT_RESET_1_CKE_0);
/* bring up clock enable */
/* tXRP < 250 ck cycles */
delay_for_n_mem_clocks(250);
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
- if (param->skip_ranks[r]) {
- /* request to skip the rank */
- continue;
- }
-
- /* set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
-
- /*
- * USER Use Mirror-ed commands for odd ranks if address
- * mirrorring is on
- */
- if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
- set_jump_as_return();
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_MRS2_MIRR, addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET_MIRR, addr);
- } else {
- set_jump_as_return();
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_MRS2, addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS3, addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS1, addr);
- set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET, addr);
- }
- set_jump_as_return();
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_ZQCL, addr);
-
- /* tZQinit = tDLLK = 512 ck cycles */
- delay_for_n_mem_clocks(512);
- }
+ rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
+ 0);
}
/*
*/
static void rw_mgr_mem_handoff(void)
{
- uint32_t r;
- uint32_t addr;
-
- debug("%s:%d\n", __func__, __LINE__);
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
- if (param->skip_ranks[r])
- /* request to skip the rank */
- continue;
- /* set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
-
- /* precharge all banks ... */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_PRECHARGE_ALL, addr);
-
- /* load up MR settings specified by user */
-
- /*
- * Use Mirror-ed commands for odd ranks if address
- * mirrorring is on
- */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
- set_jump_as_return();
- writel(RW_MGR_MRS2_MIRR, addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS0_USER_MIRR, addr);
- } else {
- set_jump_as_return();
- writel(RW_MGR_MRS2, addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS3, addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS1, addr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS0_USER, addr);
- }
- /*
- * USER need to wait tMOD (12CK or 15ns) time before issuing
- * other commands, but we will have plenty of NIOS cycles before
- * actual handoff so its okay.
- */
- }
+ rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
+ /*
+ * USER need to wait tMOD (12CK or 15ns) time before issuing
+ * other commands, but we will have plenty of NIOS cycles before
+ * actual handoff so its okay.
+ */
}
/*
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts of read commands */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x20, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_GUARANTEED_READ, addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_GUARANTEED_READ,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x20, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_GUARANTEED_READ_CONT, addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
+ writel(RW_MGR_GUARANTEED_READ_CONT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
tmp_bit_chk = 0;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, addr);
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
/ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- base_rw_mgr = readl(addr);
+ base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
if (vg == 0)
uint32_t all_ranks)
{
uint32_t r;
- uint32_t addr;
uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x20, addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT0, addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x20, addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT1, addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x04, addr);
+ writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT2, addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
- writel(0x04, addr);
+ writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT3, addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_GUARANTEED_WRITE, addr);
+ writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x10, addr);
+ writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_READ_B2B_WAIT1, addr);
+ writel(RW_MGR_READ_B2B_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x10, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_READ_B2B_WAIT2, addr);
+ writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
+ writel(RW_MGR_READ_B2B_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
if (quick_read_mode)
- writel(0x1, addr);
+ writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
/* need at least two (1+1) reads to capture failures */
else if (all_groups)
- writel(0x06, addr);
+ writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
else
- writel(0x32, addr);
+ writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_READ_B2B, addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
+ writel(RW_MGR_READ_B2B,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
if (all_groups)
writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
- addr);
+ &sdr_rw_load_mgr_regs->load_cntr3);
else
- writel(0x0, addr);
+ writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_READ_B2B, addr);
+ writel(RW_MGR_READ_B2B,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
tmp_bit_chk = 0;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, addr);
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
/ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- base_rw_mgr = readl(addr);
+ base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
if (vg == 0)
static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
{
- uint32_t addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy;
-
- writel(grp, addr);
+ writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
(*v)++;
}
uint32_t dtaps_per_ptap;
uint32_t work_bgn, work_mid, work_end;
uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
- uint32_t addr;
debug("%s:%d %u\n", __func__, __LINE__, grp);
if (found_passing_read && found_failing_read)
dtaps_per_ptap = d - initial_failing_dtap;
- addr = (u32)&sdr_reg_file->dtaps_per_ptap;
- writel(dtaps_per_ptap, addr);
+ writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
- %u = %u", __func__, __LINE__, d,
initial_failing_dtap, dtaps_per_ptap);
uint32_t p;
uint32_t d;
uint32_t r;
- uint32_t addr;
const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
(RW_MGR_MEM_DQ_PER_READ_DQS-1);
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS;
- i++, p++, d += delay_step) {
+ for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
vfifo_find_dqs_", __func__, __LINE__);
debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
write_group, read_group);
debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
- scc_mgr_set_dq_in_delay(write_group, p, d);
+ scc_mgr_set_dq_in_delay(p, d);
scc_mgr_load_dq(p);
}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
}
found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
r += NUM_RANKS_PER_SHADOW_REG) {
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
i++, p++) {
- scc_mgr_set_dq_in_delay(write_group, p, 0);
+ scc_mgr_set_dq_in_delay(p, 0);
scc_mgr_load_dq(p);
}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
}
return found;
right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
}
- addr = (u32)&sdr_scc_mgr->update;
/* Search for the left edge of the window for each bit */
for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
}
/* Reset DQ delay chains to 0 */
- scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, 0);
+ scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
sticky_bit_chk = 0;
for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
break;
}
- addr = (u32)&sdr_scc_mgr->update;
/* Search for the right edge of the window for each bit */
for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
}
scc_mgr_load_dqs(read_group);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
}
/* Check that all bits have a window */
- addr = (u32)&sdr_scc_mgr->update;
for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
%d right_edge[%u]: %d", __func__, __LINE__,
start_dqs_en);
}
scc_mgr_load_dqs(read_group);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
find edge [%u]: %d %d", __func__, __LINE__,
dqs_margin = IO_IO_IN_DELAY_MAX + 1;
dq_margin = IO_IO_IN_DELAY_MAX + 1;
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
/* add delay to bring centre of all DQ windows to the same "level" */
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
/* Use values before divide by 2 to reduce round off error */
debug_cond(DLEVEL == 2, "vfifo_center: before: \
shift_dq[%u]=%d\n", i, shift_dq);
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
temp_dq_in_delay1 = readl(addr + (p << 2));
temp_dq_in_delay2 = readl(addr + (i << 2));
debug_cond(DLEVEL == 2, "vfifo_center: after: \
shift_dq[%u]=%d\n", i, shift_dq);
final_dq[i] = temp_dq_in_delay1 + shift_dq;
- scc_mgr_set_dq_in_delay(write_group, p, final_dq[i]);
+ scc_mgr_set_dq_in_delay(p, final_dq[i]);
scc_mgr_load_dq(p);
debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
* Do not remove this line as it makes sure all of our decisions
* have been applied. Apply the update bit.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
return (dq_margin >= 0) && (dqs_margin >= 0);
}
{
uint32_t p, d, rank_bgn, sr;
uint32_t dtaps_per_ptap;
- uint32_t tmp_delay;
uint32_t bit_chk;
uint32_t grp_calibrated;
uint32_t write_group, write_test_bgn;
write_test_bgn = test_bgn;
/* USER Determine number of delay taps for each phase tap */
- dtaps_per_ptap = 0;
- tmp_delay = 0;
- while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
- dtaps_per_ptap++;
- tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- }
- dtaps_per_ptap--;
- tmp_delay = 0;
+ dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
/* update info for sims */
reg_file_set_group(read_group);
* calibrated output side yet.
*/
if (d > 0) {
- scc_mgr_apply_group_all_out_delay_add_all_ranks
- (write_group, write_test_bgn, d);
+ scc_mgr_apply_group_all_out_delay_add_all_ranks(
+ write_group, d);
}
for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
* first case).
*/
if (d > 2)
- scc_mgr_zero_group(write_group, write_test_bgn, 1);
+ scc_mgr_zero_group(write_group, 1);
return 1;
}
{
uint32_t found_one;
uint32_t bit_chk;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
rw_mgr_mem_calibrate_read_load_patterns(0, 1);
found_one = 0;
- addr = (u32)&phy_mgr_cfg->phy_rlat;
do {
- writel(gbl->curr_read_lat, addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
__func__, __LINE__, gbl->curr_read_lat);
/* reset the fifos to get pointers to known state */
- addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
if (found_one) {
/* add a fudge factor to the read latency that was determined */
gbl->curr_read_lat += 2;
- addr = (u32)&phy_mgr_cfg->phy_rlat;
- writel(gbl->curr_read_lat, addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
read_lat=%u\n", __func__, __LINE__,
gbl->curr_read_lat);
* instruction that sends out the data. We set the counter to a
* large number so that the jump is always taken.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0xFF, addr);
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
- addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
- addr);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
} else if (rw_wl_nop_cycles == 0) {
/*
* to the DQS enable instruction. We set the counter to a large
* number so that the jump is always taken.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0xFF, addr);
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
- addr);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS, addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
}
} else {
/*
* and NOT take the jump. So we set the counter to 0. The jump
* address doesn't count.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x0, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(0x0, addr);
+ writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
+ writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
/*
* CNTR 3 - Set the nop counter to the number of cycles we
* need to loop for, minus 1.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
- writel(rw_wl_nop_cycles - 1, addr);
+ writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, addr);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
}
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
- writel(0, addr);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
if (quick_write_mode)
- writel(0x08, addr);
+ writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
else
- writel(0x40, addr);
+ writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(mcc_instruction, addr);
+ writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
/*
* CNTR 1 - This is used to ensure enough time elapses
* for read data to come back.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x30, addr);
+ writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
if (test_dm) {
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, addr);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
} else {
- writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT, addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
}
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
uint32_t *bit_chk, uint32_t all_ranks)
{
- uint32_t addr;
uint32_t r;
uint32_t correct_mask_vg;
uint32_t tmp_bit_chk;
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
tmp_bit_chk = 0;
- addr = (u32)&phy_mgr_cmd->fifo_reset;
addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
tmp_bit_chk = tmp_bit_chk <<
(RW_MGR_MEM_DQ_PER_WRITE_DQS /
}
/* Search for the left edge of the window for each bit */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
- scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
+ scc_mgr_apply_group_dq_out1_delay(write_group, d);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
}
/* Reset DQ delay chains to 0 */
- scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, 0);
+ scc_mgr_apply_group_dq_out1_delay(0);
sticky_bit_chk = 0;
for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
}
/* Search for the right edge of the window for each bit */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + start_dqs);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
/* add delay to bring centre of all DQ windows to the same "level" */
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
/* Use values before divide by 2 to reduce round off error */
shift_dq = (left_edge[i] - right_edge[i] -
debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
[%u]=%d\n", __func__, __LINE__, i, shift_dq);
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
temp_dq_out1_delay = readl(addr + (i << 2));
if (shift_dq + (int32_t)temp_dq_out1_delay >
(int32_t)IO_IO_OUT1_DELAY_MAX) {
}
debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
i, shift_dq);
- scc_mgr_set_dq_out1_delay(write_group, i, temp_dq_out1_delay +
- shift_dq);
+ scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
scc_mgr_load_dq(i);
debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
/* Move DQS */
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/* Centre DM */
debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
int32_t win_best = 0;
/* Search for the/part of the window with DM shift */
- addr = (u32)&sdr_scc_mgr->update;
for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
- scc_mgr_apply_group_dm_out1_delay(write_group, d);
- writel(0, addr);
+ scc_mgr_apply_group_dm_out1_delay(d);
+ writel(0, &sdr_scc_mgr->update);
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
/* Reset DM delay chains to 0 */
- scc_mgr_apply_group_dm_out1_delay(write_group, 0);
+ scc_mgr_apply_group_dm_out1_delay(0);
/*
* Check to see if the current window nudges up aganist 0 delay.
}
/* Search for the/part of the window with DQS shifts */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
/*
* Note: This only shifts DQS, so are we limiting ourselve to
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + new_dqs);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
0)) {
else
dm_margin = left_edge[0] - mid;
- scc_mgr_apply_group_dm_out1_delay(write_group, mid);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ scc_mgr_apply_group_dm_out1_delay(mid);
+ writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
dm_margin=%d\n", __func__, __LINE__, left_edge[0],
* Do not remove this line as it makes sure all of our
* decisions have been applied.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
}
static void mem_precharge_and_activate(void)
{
uint32_t r;
- uint32_t addr;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
if (param->skip_ranks[r]) {
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
/* precharge all banks ... */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_PRECHARGE_ALL, addr);
+ writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x0F, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1, addr);
+ writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x0F, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2, addr);
+ writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* activate rows */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_ACTIVATE_0_AND_1, addr);
+ writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
}
uint32_t rlat, wlat;
uint32_t rw_wl_nop_cycles;
uint32_t max_latency;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* read in write and read latency */
- addr = (u32)&data_mgr->t_wl_add;
- wlat = readl(addr);
+ wlat = readl(&data_mgr->t_wl_add);
+ wlat += readl(&data_mgr->mem_t_add);
- addr = (u32)&data_mgr->mem_t_add;
- wlat += readl(addr);
/* WL for hard phy does not include additive latency */
/*
*/
wlat = wlat + 1;
- addr = (u32)&data_mgr->t_rl_add;
- rlat = readl(addr);
+ rlat = readl(&data_mgr->t_rl_add);
rw_wl_nop_cycles = wlat - 2;
gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
if (gbl->curr_read_lat > max_latency)
gbl->curr_read_lat = max_latency;
- addr = (u32)&phy_mgr_cfg->phy_rlat;
- writel(gbl->curr_read_lat, addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
/* advertise write latency */
gbl->curr_write_lat = wlat;
- addr = (u32)&phy_mgr_cfg->afi_wlat;
- writel(wlat - 2, addr);
+ writel(wlat - 2, &phy_mgr_cfg->afi_wlat);
/* initialize bit slips */
mem_precharge_and_activate();
{
uint32_t vfifo_offset;
uint32_t i, j, r;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* Need to update every shadow register set used by the interface */
scc_mgr_set_dqdqs_output_phase(i, (1.25 *
IO_DLL_CHAIN_LENGTH - 2));
}
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(0xff, addr);
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0xff, addr);
+ writel(0xff, &sdr_scc_mgr->dqs_ena);
+ writel(0xff, &sdr_scc_mgr->dqs_io_ena);
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
- writel(i, addr);
+ writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
}
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, addr);
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, addr);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0xff, &sdr_scc_mgr->dq_ena);
+ writel(0xff, &sdr_scc_mgr->dm_ena);
+ writel(0, &sdr_scc_mgr->update);
}
/* Compensate for simulation model behaviour */
scc_mgr_set_dqs_bus_in_delay(i, 10);
scc_mgr_load_dqs(i);
}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* ArriaV has hard FIFOs that can only be initialized by incrementing
* in sequencer.
*/
vfifo_offset = CALIB_VFIFO_OFFSET;
- addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy;
for (j = 0; j < vfifo_offset; j++) {
- writel(0xff, addr);
+ writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
}
- addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
/*
* For ACV with hard lfifo, we get the skip-cal setting from
* generation-time constant.
*/
gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
- addr = (u32)&phy_mgr_cfg->phy_rlat;
- writel(gbl->curr_read_lat, addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
}
/* Memory calibration entry point */
uint32_t failing_groups = 0;
uint32_t group_failed = 0;
uint32_t sr_failed = 0;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* Initialize the data settings */
mem_config();
- uint32_t bypass_mode = 0x1;
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
- writel(i, addr);
- scc_set_bypass_mode(i, bypass_mode);
+ writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
+ /* Only needed once to set all groups, pins, DQ, DQS, DM. */
+ if (i == 0)
+ scc_mgr_set_hhp_extras();
+
+ scc_set_bypass_mode(i);
}
if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
if (current_run == 0)
continue;
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
- writel(write_group, addr);
- scc_mgr_zero_group(write_group, write_test_bgn,
- 0);
+ writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
+ scc_mgr_zero_group(write_group, 0);
for (read_group = write_group *
RW_MGR_MEM_IF_READ_DQS_WIDTH /
* Do not remove this line as it makes sure all of our decisions
* have been applied.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
return 1;
}
{
uint32_t pass;
uint32_t debug_info;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* Reset pass/fail status shown on afi_cal_success/fail */
- addr = (u32)&phy_mgr_cfg->cal_status;
- writel(PHY_MGR_CAL_RESET, addr);
+ writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
- addr = SDR_CTRLGRP_ADDRESS;
/* stop tracking manger */
- uint32_t ctrlcfg = readl(addr);
+ uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg);
- addr = SDR_CTRLGRP_ADDRESS;
- writel(ctrlcfg & 0xFFBFFFFF, addr);
+ writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
initialize();
rw_mgr_mem_initialize();
pass = mem_calibrate();
mem_precharge_and_activate();
- addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
/*
* Handoff:
* 0: AFI Mux Select
* 1: DDIO Mux Select
*/
- addr = (u32)&phy_mgr_cfg->mux_sel;
- writel(0x2, addr);
+ writel(0x2, &phy_mgr_cfg->mux_sel);
}
- addr = SDR_CTRLGRP_ADDRESS;
- writel(ctrlcfg, addr);
+ writel(ctrlcfg, &sdr_ctrl->ctrl_cfg);
if (pass) {
printf("%s: CALIBRATION PASSED\n", __FILE__);
/* Update the FOM in the register file */
debug_info = gbl->fom_in;
debug_info |= gbl->fom_out << 8;
- addr = (u32)&sdr_reg_file->fom;
- writel(debug_info, addr);
+ writel(debug_info, &sdr_reg_file->fom);
- addr = (u32)&phy_mgr_cfg->cal_debug_info;
- writel(debug_info, addr);
- addr = (u32)&phy_mgr_cfg->cal_status;
- writel(PHY_MGR_CAL_SUCCESS, addr);
+ writel(debug_info, &phy_mgr_cfg->cal_debug_info);
+ writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
} else {
printf("%s: CALIBRATION FAILED\n", __FILE__);
debug_info |= gbl->error_substage << 8;
debug_info |= gbl->error_group << 16;
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(debug_info, addr);
- addr = (u32)&phy_mgr_cfg->cal_debug_info;
- writel(debug_info, addr);
- addr = (u32)&phy_mgr_cfg->cal_status;
- writel(PHY_MGR_CAL_FAIL, addr);
+ writel(debug_info, &sdr_reg_file->failing_stage);
+ writel(debug_info, &phy_mgr_cfg->cal_debug_info);
+ writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
/* Update the failing group/stage in the register file */
debug_info = gbl->error_stage;
debug_info |= gbl->error_substage << 8;
debug_info |= gbl->error_group << 16;
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(debug_info, addr);
+ writel(debug_info, &sdr_reg_file->failing_stage);
}
return pass;
}
+/**
+ * hc_initialize_rom_data() - Initialize ROM data
+ *
+ * Initialize ROM data.
+ */
static void hc_initialize_rom_data(void)
{
- uint32_t i;
- uint32_t addr;
+ u32 i, addr;
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
- for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++) {
- uint32_t data = inst_rom_init[i];
- writel(data, addr + (i << 2));
- }
+ for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
+ writel(inst_rom_init[i], addr + (i << 2));
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
- for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++) {
- uint32_t data = ac_rom_init[i];
- writel(data, addr + (i << 2));
- }
+ for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
+ writel(ac_rom_init[i], addr + (i << 2));
}
+/**
+ * initialize_reg_file() - Initialize SDR register file
+ *
+ * Initialize SDR register file.
+ */
static void initialize_reg_file(void)
{
- uint32_t addr;
-
/* Initialize the register file with the correct data */
- addr = (u32)&sdr_reg_file->signature;
- writel(REG_FILE_INIT_SEQ_SIGNATURE, addr);
-
- addr = (u32)&sdr_reg_file->debug_data_addr;
- writel(0, addr);
-
- addr = (u32)&sdr_reg_file->cur_stage;
- writel(0, addr);
-
- addr = (u32)&sdr_reg_file->fom;
- writel(0, addr);
-
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(0, addr);
-
- addr = (u32)&sdr_reg_file->debug1;
- writel(0, addr);
-
- addr = (u32)&sdr_reg_file->debug2;
- writel(0, addr);
+ writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
+ writel(0, &sdr_reg_file->debug_data_addr);
+ writel(0, &sdr_reg_file->cur_stage);
+ writel(0, &sdr_reg_file->fom);
+ writel(0, &sdr_reg_file->failing_stage);
+ writel(0, &sdr_reg_file->debug1);
+ writel(0, &sdr_reg_file->debug2);
}
+/**
+ * initialize_hps_phy() - Initialize HPS PHY
+ *
+ * Initialize HPS PHY.
+ */
static void initialize_hps_phy(void)
{
uint32_t reg;
- uint32_t addr;
/*
* Tracking also gets configured here because it's in the
* same register.
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
trk_sample_count);
- addr = SDR_CTRLGRP_ADDRESS;
- writel(reg, addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl0);
reg = 0;
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
trk_long_idle_sample_count);
- writel(reg, addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl1);
reg = 0;
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
trk_long_idle_sample_count >>
SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
- writel(reg, addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl2);
}
static void initialize_tracking(void)
uint32_t trk_sample_count = 7500;
uint32_t dtaps_per_ptap;
uint32_t tmp_delay;
- uint32_t addr;
/*
* compute usable version of value in case we skip full
concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
/* Initialize the register file with the correct data */
- addr = (u32)&sdr_reg_file->dtaps_per_ptap;
- writel(dtaps_per_ptap, addr);
-
- addr = (u32)&sdr_reg_file->trk_sample_count;
- writel(trk_sample_count, addr);
-
- addr = (u32)&sdr_reg_file->trk_longidle;
- writel(concatenated_longidle, addr);
-
- addr = (u32)&sdr_reg_file->delays;
- writel(concatenated_delays, addr);
-
- addr = (u32)&sdr_reg_file->trk_rw_mgr_addr;
- writel(concatenated_rw_addr, addr);
-
- addr = (u32)&sdr_reg_file->trk_read_dqs_width;
- writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, addr);
-
- addr = (u32)&sdr_reg_file->trk_rfsh;
- writel(concatenated_refresh, addr);
+ writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
+ writel(trk_sample_count, &sdr_reg_file->trk_sample_count);
+ writel(concatenated_longidle, &sdr_reg_file->trk_longidle);
+ writel(concatenated_delays, &sdr_reg_file->delays);
+ writel(concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr);
+ writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, &sdr_reg_file->trk_read_dqs_width);
+ writel(concatenated_refresh, &sdr_reg_file->trk_rfsh);
}
int sdram_calibration_full(void)
projects / oweals / u-boot.git / blobdiff