ddr: altera: Clean up find_vfifo_read()

[oweals/u-boot.git] / drivers / ddr / altera / sdram.c

diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 5d8fed36a85374f69aa51595671e57073035f7d5..474df4265417eb6d9d20a8248864d1c566c8d418 100644 (file)
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -8,19 +8,37 @@
 #include <watchdog.h>
 #include <asm/arch/fpga_manager.h>
 #include <asm/arch/sdram.h>
-#include <asm/arch/sdram_config.h>
 #include <asm/arch/system_manager.h>
 #include <asm/io.h>
 
+/*
+ * FIXME: This path is temporary until the SDRAM driver gets
+ *        a proper thorough cleanup.
+ */
+#include "../../../board/altera/socfpga/qts/sdram_config.h"
+
 /* define constant for 4G memory - used for SDRAM errata workaround */
 #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct sdram_prot_rule {
+       u64     sdram_start;    /* SDRAM start address */
+       u64     sdram_end;      /* SDRAM end address */
+       u32     rule;           /* SDRAM protection rule number: 0-19 */
+       int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
+
+       u32     security;
+       u32     portmask;
+       u32     result;
+       u32     lo_prot_id;
+       u32     hi_prot_id;
+};
+
 static struct socfpga_system_manager *sysmgr_regs =
        (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 static struct socfpga_sdr_ctrl *sdr_ctrl =
-       (struct socfpga_sdr_ctrl *)(SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_ADDRESS);
+       (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 
 static int compute_errata_rows(unsigned long long memsize, int cs, int width,
                               int rows, int banks, int cols)
@@ -521,7 +539,7 @@ static void set_sdr_mp_threshold(void)
 
        clrsetbits_le32(&sdr_ctrl->mp_threshold1,
                        SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
-                       SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK <<
+                       CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
                        SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
 
        clrsetbits_le32(&sdr_ctrl->mp_threshold2,