clk: sifive: Sync-up DT bindings header with upstream Linux

[oweals/u-boot.git] / drivers / clk / sifive / fu540-prci.c

diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index 56084db2e6ac2ab89b185233c3dcc26872d5c83b..ceb318e062bc18a125a700790fd2e3683b187cf8 100644 (file)
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -38,7 +38,7 @@
 
 #include <linux/math64.h>
 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
-#include <dt-bindings/clk/sifive-fu540-prci.h>
+#include <dt-bindings/clock/sifive-fu540-prci.h>
 
 /*
  * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
@@ -174,7 +174,7 @@ struct __prci_data {
  * bypass mux is not glitchless.
  */
 struct __prci_wrpll_data {
-       struct analogbits_wrpll_cfg c;
+       struct wrpll_cfg c;
        void (*bypass)(struct __prci_data *pd);
        void (*no_bypass)(struct __prci_data *pd);
        u8 cfg0_offs;
@@ -244,7 +244,7 @@ static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
 
 /**
  * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
- * @c: ptr to a struct analogbits_wrpll_cfg record to write config into
+ * @c: ptr to a struct wrpll_cfg record to write config into
  * @r: value read from the PRCI PLL configuration register
  *
  * Given a value @r read from an FU540 PRCI PLL configuration register,
@@ -256,7 +256,7 @@ static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
  *
  * Context: Any context.
  */
-static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
+static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
 {
        u32 v;
 
@@ -287,7 +287,7 @@ static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
 
 /**
  * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
- * @c: pointer to a struct analogbits_wrpll_cfg record containing the PLL's cfg
+ * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
  *
  * Using a set of WRPLL configuration values pointed to by @c,
  * assemble a PRCI PLL configuration register value, and return it to
@@ -300,7 +300,7 @@ static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
  * Returns: a value suitable for writing into a PRCI PLL configuration
  *          register
  */
-static u32 __prci_wrpll_pack(struct analogbits_wrpll_cfg *c)
+static u32 __prci_wrpll_pack(struct wrpll_cfg *c)
 {
        u32 r = 0;
 
@@ -348,11 +348,11 @@ static void __prci_wrpll_read_cfg(struct __prci_data *pd,
  */
 static void __prci_wrpll_write_cfg(struct __prci_data *pd,
                                   struct __prci_wrpll_data *pwd,
-                                  struct analogbits_wrpll_cfg *c)
+                                  struct wrpll_cfg *c)
 {
        __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
 
-       memcpy(&pwd->c, c, sizeof(struct analogbits_wrpll_cfg));
+       memcpy(&pwd->c, c, sizeof(struct wrpll_cfg));
 }
 
 /* Core clock mux control */
@@ -403,7 +403,7 @@ static unsigned long sifive_fu540_prci_wrpll_recalc_rate(
 {
        struct __prci_wrpll_data *pwd = pc->pwd;
 
-       return analogbits_wrpll_calc_output_rate(&pwd->c, parent_rate);
+       return wrpll_calc_output_rate(&pwd->c, parent_rate);
 }
 
 static unsigned long sifive_fu540_prci_wrpll_round_rate(
@@ -412,13 +412,13 @@ static unsigned long sifive_fu540_prci_wrpll_round_rate(
                                                unsigned long *parent_rate)
 {
        struct __prci_wrpll_data *pwd = pc->pwd;
-       struct analogbits_wrpll_cfg c;
+       struct wrpll_cfg c;
 
        memcpy(&c, &pwd->c, sizeof(c));
 
-       analogbits_wrpll_configure_for_rate(&c, rate, *parent_rate);
+       wrpll_configure_for_rate(&c, rate, *parent_rate);
 
-       return analogbits_wrpll_calc_output_rate(&c, *parent_rate);
+       return wrpll_calc_output_rate(&c, *parent_rate);
 }
 
 static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
@@ -429,7 +429,7 @@ static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
        struct __prci_data *pd = pc->pd;
        int r;
 
-       r = analogbits_wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
+       r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
        if (r)
                return -ERANGE;
 
@@ -438,7 +438,7 @@ static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
 
        __prci_wrpll_write_cfg(pd, pwd, &pwd->c);
 
-       udelay(analogbits_wrpll_calc_max_lock_us(&pwd->c));
+       udelay(wrpll_calc_max_lock_us(&pwd->c));
 
        if (pwd->no_bypass)
                pwd->no_bypass(pd);