rockchip: clk: Add rk3368 SARADC clock support

[oweals/u-boot.git] / drivers / clk / rockchip / clk_rv1108.c

diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index 0a3ba3bff9f7cd4567cd8139c29c154f2500e799..86e73e414cf971bfe138b58919665ae2d28c5d48 100644 (file)
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <bitfield.h>
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
@@ -25,9 +26,6 @@ enum {
        OUTPUT_MIN_HZ   = 24 * 1000000,
 };
 
-#define RATE_TO_DIV(input_rate, output_rate) \
-       ((input_rate) / (output_rate) - 1);
-
 #define DIV_TO_RATE(input_rate, div)   ((input_rate) / ((div) + 1))
 
 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
@@ -39,10 +37,7 @@ enum {
                         #hz "Hz cannot be hit with PLL "\
                         "divisors on line " __stringify(__LINE__));
 
-/* use interge mode*/
-static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
-static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
-
+/* use integer mode */
 static inline int rv1108_pll_id(enum rk_clk_id clk_id)
 {
        int id = 0;
@@ -136,6 +131,31 @@ static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)
        return DIV_TO_RATE(pll_rate, div);
 }
 
+static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)
+{
+       u32 div, val;
+
+       val = readl(&cru->clksel_con[22]);
+       div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
+                              CLK_SARADC_DIV_CON_WIDTH);
+
+       return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
+{
+       int src_clk_div;
+
+       src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
+       assert(src_clk_div < 128);
+
+       rk_clrsetreg(&cru->clksel_con[22],
+                    CLK_SARADC_DIV_CON_MASK,
+                    src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
+
+       return rv1108_saradc_get_clk(cru);
+}
+
 static ulong rv1108_clk_get_rate(struct clk *clk)
 {
        struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
@@ -143,6 +163,8 @@ static ulong rv1108_clk_get_rate(struct clk *clk)
        switch (clk->id) {
        case 0 ... 63:
                return rkclk_pll_get_rate(priv->cru, clk->id);
+       case SCLK_SARADC:
+               return rv1108_saradc_get_clk(priv->cru);
        default:
                return -ENOENT;
        }
@@ -160,6 +182,9 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
        case SCLK_SFC:
                new_rate = rv1108_sfc_set_clk(priv->cru, rate);
                break;
+       case SCLK_SARADC:
+               new_rate = rv1108_saradc_set_clk(priv->cru, rate);
+               break;
        default:
                return -ENOENT;
        }