#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
+#include <malloc.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3328.h>
u32 hclk_div;
u32 pclk_div;
+ rk3328_configure_cpu(cru, APLL_600_MHZ);
+
/* configure gpll cpll */
rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
sys_child->priv = priv;
}
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
ret = offsetof(struct rk3328_cru, softrst_con[0]);
ret = rockchip_reset_bind(dev, ret, 12);
if (ret)