Merge git://git.denx.de/u-boot-socfpga

[oweals/u-boot.git] / drivers / clk / rockchip / clk_rk322x.c

diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index fdeb816e2316bb1d90a89d6a134875641151cd2b..ff52b5522903ea026c779cbc93e4faf9e1234366 100644 (file)
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -26,9 +26,6 @@ enum {
        OUTPUT_MIN_HZ   = 24 * 1000000,
 };
 
-#define RATE_TO_DIV(input_rate, output_rate) \
-       ((input_rate) / (output_rate) - 1);
-
 #define DIV_TO_RATE(input_rate, div)   ((input_rate) / ((div) + 1))
 
 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
@@ -120,16 +117,16 @@ static void rkclk_init(struct rk322x_cru *cru)
                     pclk_div << CORE_PERI_DIV_SHIFT);
 
        /*
-        * select apll as pd_bus bus clock source and
+        * select gpll as pd_bus bus clock source and
         * set up dependent divisors for PCLK/HCLK and ACLK clocks.
         */
        aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
        assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
 
-       pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
+       pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
        assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
 
-       hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
+       hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
        assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
 
        rk_clrsetreg(&cru->cru_clksel_con[0],
@@ -239,7 +236,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
        }
 
        src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
-       return DIV_TO_RATE(src_rate, div);
+       return DIV_TO_RATE(src_rate, div) / 2;
 }
 
 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
@@ -250,11 +247,12 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
 
        debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
 
-       /* mmc clock auto divide 2 in internal */
-       src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
+       /* mmc clock defaulg div 2 internal, need provide double in cru */
+       src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
 
-       if (src_clk_div > 0x7f) {
-               src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
+       if (src_clk_div > 128) {
+               src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+               assert(src_clk_div - 1 < 128);
                mux = EMMC_SEL_24M;
        } else {
                mux = EMMC_SEL_GPLL;
@@ -387,11 +385,22 @@ static int rk322x_clk_probe(struct udevice *dev)
 static int rk322x_clk_bind(struct udevice *dev)
 {
        int ret;
+       struct udevice *sys_child;
+       struct sysreset_reg *priv;
 
        /* The reset driver does not have a device node, so bind it here */
-       ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev);
-       if (ret)
-               debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
+       ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+                                &sys_child);
+       if (ret) {
+               debug("Warning: No sysreset driver: ret=%d\n", ret);
+       } else {
+               priv = malloc(sizeof(struct sysreset_reg));
+               priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
+                                                   cru_glb_srst_fst_value);
+               priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
+                                                   cru_glb_srst_snd_value);
+               sys_child->priv = priv;
+       }
 
        return 0;
 }