rockchip: clk: Add rk3368 SARADC clock support

[oweals/u-boot.git] / drivers / clk / rockchip / clk_rk322x.c

diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index fdeb816e2316bb1d90a89d6a134875641151cd2b..d7f6a3c313e6c86143dc3931fc00196981d8b534 100644 (file)
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -26,9 +26,6 @@ enum {
        OUTPUT_MIN_HZ   = 24 * 1000000,
 };
 
-#define RATE_TO_DIV(input_rate, output_rate) \
-       ((input_rate) / (output_rate) - 1);
-
 #define DIV_TO_RATE(input_rate, div)   ((input_rate) / ((div) + 1))
 
 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
@@ -239,7 +236,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
        }
 
        src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
-       return DIV_TO_RATE(src_rate, div);
+       return DIV_TO_RATE(src_rate, div) / 2;
 }
 
 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
@@ -250,11 +247,12 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
 
        debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
 
-       /* mmc clock auto divide 2 in internal */
-       src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
+       /* mmc clock defaulg div 2 internal, need provide double in cru */
+       src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
 
-       if (src_clk_div > 0x7f) {
-               src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
+       if (src_clk_div > 128) {
+               src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+               assert(src_clk_div - 1 < 128);
                mux = EMMC_SEL_24M;
        } else {
                mux = EMMC_SEL_GPLL;