Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

[oweals/u-boot.git] / drivers / clk / clk_zynq.c

diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index a070f01ec8de176e8f67d97b2684191117d385cd..a699a3664c335ac738bca1bbaf880f3e786337c4 100644 (file)
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -1,16 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG
  * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
  *
  * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
  * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <clk-uclass.h>
 #include <dm.h>
+#include <log.h>
+#include <dm/device_compat.h>
 #include <dm/lists.h>
 #include <errno.h>
 #include <asm/io.h>
@@ -48,6 +49,9 @@ enum zynq_clk_rclk {mio_clk, emio_clk};
 
 struct zynq_clk_priv {
        ulong ps_clk_freq;
+#ifndef CONFIG_SPL_BUILD
+       struct clk gem_emio_clk[2];
+#endif
 };
 
 static void *zynq_clk_get_register(enum zynq_clk id)
@@ -267,9 +271,15 @@ static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv,
 #ifndef CONFIG_SPL_BUILD
 static ulong zynq_clk_get_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id)
 {
+       struct clk *parent;
+
        if (zynq_clk_get_gem_rclk(id) == mio_clk)
                return zynq_clk_get_peripheral_rate(priv, id, true);
 
+       parent = &priv->gem_emio_clk[id - gem0_clk];
+       if (parent->dev)
+               return clk_get_rate(parent);
+
        debug("%s: gem%d emio rx clock source unknown\n", __func__,
              id - gem0_clk);
 
@@ -340,9 +350,15 @@ static ulong zynq_clk_set_peripheral_rate(struct zynq_clk_priv *priv,
 static ulong zynq_clk_set_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id,
                                   ulong rate)
 {
+       struct clk *parent;
+
        if (zynq_clk_get_gem_rclk(id) == mio_clk)
                return zynq_clk_set_peripheral_rate(priv, id, rate, true);
 
+       parent = &priv->gem_emio_clk[id - gem0_clk];
+       if (parent->dev)
+               return clk_set_rate(parent, rate);
+
        debug("%s: gem%d emio rx clock source unknown\n", __func__,
              id - gem0_clk);
 
@@ -379,7 +395,7 @@ static ulong zynq_clk_get_rate(struct clk *clk)
                return zynq_clk_get_peripheral_rate(priv, id, two_divs);
        case dma_clk:
                return zynq_clk_get_cpu_rate(priv, cpu_2x_clk);
-       case usb0_aper_clk ... smc_aper_clk:
+       case usb0_aper_clk ... swdt_clk:
                return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
        default:
                return -ENXIO;
@@ -420,6 +436,8 @@ static ulong zynq_clk_get_rate(struct clk *clk)
        case lqspi_clk ... pcap_clk:
        case sdio0_clk ... spi1_clk:
                return zynq_clk_get_peripheral_rate(priv, id, 0);
+       case i2c0_aper_clk ... i2c1_aper_clk:
+               return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
        default:
                return -ENXIO;
        }
@@ -436,8 +454,22 @@ static struct clk_ops zynq_clk_ops = {
 static int zynq_clk_probe(struct udevice *dev)
 {
        struct zynq_clk_priv *priv = dev_get_priv(dev);
+#ifndef CONFIG_SPL_BUILD
+       unsigned int i;
+       char name[16];
+       int ret;
+
+       for (i = 0; i < 2; i++) {
+               sprintf(name, "gem%d_emio_clk", i);
+               ret = clk_get_by_name(dev, name, &priv->gem_emio_clk[i]);
+               if (ret < 0 && ret != -ENODATA) {
+                       dev_err(dev, "failed to get %s clock\n", name);
+                       return ret;
+               }
+       }
+#endif
 
-       priv->ps_clk_freq = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+       priv->ps_clk_freq = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
                                            "ps-clk-frequency", 33333333UL);
 
        return 0;
@@ -452,7 +484,6 @@ U_BOOT_DRIVER(zynq_clk) = {
        .name           = "zynq_clk",
        .id             = UCLASS_CLK,
        .of_match       = zynq_clk_ids,
-       .flags          = DM_FLAG_PRE_RELOC,
        .ops            = &zynq_clk_ops,
        .priv_auto_alloc_size = sizeof(struct zynq_clk_priv),
        .probe          = zynq_clk_probe,