+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
- *
- * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
*/
#include <common.h>
#define TIMEOUT_200MS 200000
#define TIMEOUT_1S 1000000
+/* STGEN registers */
+#define STGENC_CNTCR 0x00
+#define STGENC_CNTSR 0x04
+#define STGENC_CNTCVL 0x08
+#define STGENC_CNTCVU 0x0C
+#define STGENC_CNTFID0 0x20
+
+#define STGENC_CNTCR_EN BIT(0)
+
/* RCC registers */
#define RCC_OCENSETR 0x0C
#define RCC_OCENCLRR 0x10
#define RCC_QSPICKSELR 0x900
#define RCC_FMCCKSELR 0x904
#define RCC_USBCKSELR 0x91C
+#define RCC_DSICKSELR 0x924
+#define RCC_ADCCKSELR 0x928
#define RCC_MP_APB1ENSETR 0xA00
#define RCC_MP_APB2ENSETR 0XA08
+#define RCC_MP_APB3ENSETR 0xA10
#define RCC_MP_AHB2ENSETR 0xA18
+#define RCC_MP_AHB3ENSETR 0xA20
#define RCC_MP_AHB4ENSETR 0xA28
/* used for most of SELR register */
#define RCC_BDCR_LSEON BIT(0)
#define RCC_BDCR_LSEBYP BIT(1)
#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_DIGBYP BIT(3)
#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
#define RCC_BDCR_LSEDRV_SHIFT 4
#define RCC_BDCR_LSECSSON BIT(8)
#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
-/* used for ALL PLLNCFGR2 registers */
+/* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
+#define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
-#define RCC_PLLNCFGR2_DIVP_SHIFT 0
+#define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
-#define RCC_PLLNCFGR2_DIVQ_SHIFT 8
+#define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
-#define RCC_PLLNCFGR2_DIVR_SHIFT 16
+#define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
/* used for ALL PLLNFRACR registers */
/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
#define RCC_OCENR_HSION BIT(0)
#define RCC_OCENR_CSION BIT(4)
+#define RCC_OCENR_DIGBYP BIT(7)
#define RCC_OCENR_HSEON BIT(8)
#define RCC_OCENR_HSEBYP BIT(10)
#define RCC_OCENR_HSECSSON BIT(11)
_CK_PER,
_CK_MPU,
_CK_MCU,
+ _DSI_PHY,
_PARENT_NB,
_UNKNOWN_ID = 0xff,
};
_USBPHY_SEL,
_USBO_SEL,
_STGEN_SEL,
+ _DSI_SEL,
+ _ADC12_SEL,
_PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff,
};
STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
+
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
+ STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
+
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
- STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
- STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
+static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
+static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
+ STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
+ STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
};
#ifdef STM32MP1_CLOCK_TREE_INIT
[_CK_PER] = "CK_PER",
[_CK_MPU] = "CK_MPU",
[_CK_MCU] = "CK_MCU",
- [_USB_PHY_48] = "USB_PHY_48"
+ [_USB_PHY_48] = "USB_PHY_48",
+ [_DSI_PHY] = "DSI_PHY_PLL",
};
static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
[_FMC_SEL] = "FMC",
[_USBPHY_SEL] = "USBPHY",
[_USBO_SEL] = "USBO",
- [_STGEN_SEL] = "STGEN"
+ [_STGEN_SEL] = "STGEN",
+ [_DSI_SEL] = "DSI",
+ [_ADC12_SEL] = "ADC12",
};
#endif
return -EINVAL;
}
-static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
- int pll_id, int div_id)
+static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
+ int pll_id)
{
const struct stm32mp1_clk_pll *pll = priv->data->pll;
- int divm, divn, divy, src;
- ulong refclk, dfout;
- u32 selr, cfgr1, cfgr2, fracr;
- const u8 shift[_DIV_NB] = {
- [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
- [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
- [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
-
- debug("%s(%d, %d)\n", __func__, pll_id, div_id);
- if (div_id > _DIV_NB)
- return 0;
+ u32 selr;
+ int src;
+ ulong refclk;
+ /* Get current refclk */
selr = readl(priv->base + pll[pll_id].rckxselr);
+ src = selr & RCC_SELR_SRC_MASK;
+
+ refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
+ debug("PLL%d : selr=%x refclk = %d kHz\n",
+ pll_id, selr, (u32)(refclk / 1000));
+
+ return refclk;
+}
+
+/*
+ * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
+ * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
+ * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
+ * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
+ */
+static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
+ int pll_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ int divm, divn;
+ ulong refclk, fvco;
+ u32 cfgr1, fracr;
+
cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
- cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
fracr = readl(priv->base + pll[pll_id].pllxfracr);
- debug("PLL%d : selr=%x cfgr1=%x cfgr2=%x fracr=%x\n",
- pll_id, selr, cfgr1, cfgr2, fracr);
-
divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
- divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
-
- debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
- src = selr & RCC_SELR_SRC_MASK;
- refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
+ debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
+ pll_id, cfgr1, fracr, divn, divm);
- debug(" refclk = %d kHz\n", (u32)(refclk / 1000));
+ refclk = pll_get_fref_ck(priv, pll_id);
- /*
- * For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
- * So same final result than PLL2 et 4
- * with FRACV :
- * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
- * / (DIVM + 1) * (DIVy + 1)
+ /* with FRACV :
+ * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
* without FRACV
- * Fck_pll_y = Fck_ref * ((DIVN + 1) / (DIVM + 1) *(DIVy + 1)
+ * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
*/
if (fracr & RCC_PLLNFRACR_FRACLE) {
u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
>> RCC_PLLNFRACR_FRACV_SHIFT;
- dfout = (ulong)lldiv((unsigned long long)refclk *
+ fvco = (ulong)lldiv((unsigned long long)refclk *
(((divn + 1) << 13) + fracv),
- ((unsigned long long)(divm + 1) *
- (divy + 1)) << 13);
+ ((unsigned long long)(divm + 1)) << 13);
} else {
- dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1));
+ fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
}
+ debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
+
+ return fvco;
+}
+
+static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
+ int pll_id, int div_id)
+{
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ int divy;
+ ulong dfout;
+ u32 cfgr2;
+
+ debug("%s(%d, %d)\n", __func__, pll_id, div_id);
+ if (div_id >= _DIV_NB)
+ return 0;
+
+ cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
+ divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
+
+ debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
+
+ dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
debug(" => dfout = %d kHz\n", (u32)(dfout / 1000));
return dfout;
case _USB_PHY_48:
clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
break;
-
+ case _DSI_PHY:
+ {
+ struct clk clk;
+ struct udevice *dev = NULL;
+
+ if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
+ &dev)) {
+ if (clk_request(dev, &clk)) {
+ pr_err("ck_dsi_phy request");
+ } else {
+ clk.id = 0;
+ clock = clk_get_rate(&clk);
+ }
+ }
+ break;
+ }
default:
break;
}
return ret;
}
-static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
+static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
+ int lsedrv)
{
u32 value;
- if (bypass)
+ if (digbyp)
+ setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
+
+ if (bypass || digbyp)
setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
/*
stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
}
-static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
+static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
{
- if (bypass)
+ if (digbyp)
+ setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_DIGBYP);
+ if (bypass || digbyp)
setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
return ret;
}
+static void stgen_config(struct stm32mp1_clk_priv *priv)
+{
+ int p;
+ u32 stgenc, cntfid0;
+ ulong rate;
+
+ stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN);
+
+ cntfid0 = readl(stgenc + STGENC_CNTFID0);
+ p = stm32mp1_clk_get_parent(priv, STGEN_K);
+ rate = stm32mp1_clk_get(priv, p);
+
+ if (cntfid0 != rate) {
+ pr_debug("System Generic Counter (STGEN) update\n");
+ clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
+ writel(0x0, stgenc + STGENC_CNTCVL);
+ writel(0x0, stgenc + STGENC_CNTCVU);
+ writel(rate, stgenc + STGENC_CNTFID0);
+ setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
+
+ __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
+
+ /* need to update gd->arch.timer_rate_hz with new frequency */
+ timer_init();
+ pr_debug("gd->arch.timer_rate_hz = %x\n",
+ (u32)gd->arch.timer_rate_hz);
+ pr_debug("Tick = %x\n", (u32)(get_ticks()));
+ }
+}
+
static int set_clkdiv(unsigned int clkdiv, u32 address)
{
u32 val;
stm32mp1_lsi_set(rcc, 1);
if (priv->osc[_LSE]) {
- int bypass;
- int lsedrv;
+ int bypass, digbyp, lsedrv;
struct udevice *dev = priv->osc_dev[_LSE];
bypass = dev_read_bool(dev, "st,bypass");
+ digbyp = dev_read_bool(dev, "st,digbypass");
lse_css = dev_read_bool(dev, "st,css");
lsedrv = dev_read_u32_default(dev, "st,drive",
LSEDRV_MEDIUM_HIGH);
- stm32mp1_lse_enable(rcc, bypass, lsedrv);
+ stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
}
if (priv->osc[_HSE]) {
- int bypass, css;
+ int bypass, digbyp, css;
struct udevice *dev = priv->osc_dev[_HSE];
bypass = dev_read_bool(dev, "st,bypass");
+ digbyp = dev_read_bool(dev, "st,digbypass");
css = dev_read_bool(dev, "st,css");
- stm32mp1_hse_enable(rcc, bypass, css);
+ stm32mp1_hse_enable(rcc, bypass, digbyp, css);
}
/* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
* => switch on CSI even if node is not present in device tree
/* configure HSIDIV */
debug("configure HSIDIV\n");
- if (priv->osc[_HSI])
+ if (priv->osc[_HSI]) {
stm32mp1_hsidiv(rcc, priv->osc[_HSI]);
+ stgen_config(priv);
+ }
/* select DIV */
debug("select DIV\n");
pkcs_config(priv, CLK_CKPER_DISABLED);
}
+ /* STGEN clock source can change with CLK_STGEN_XXX */
+ stgen_config(priv);
+
debug("oscillator off\n");
/* switch OFF HSI if not found in device-tree */
if (!priv->osc[_HSI])
}
#endif /* STM32MP1_CLOCK_TREE_INIT */
+static int pll_set_output_rate(struct udevice *dev,
+ int pll_id,
+ int div_id,
+ unsigned long clk_rate)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
+ const struct stm32mp1_clk_pll *pll = priv->data->pll;
+ u32 pllxcr = priv->base + pll[pll_id].pllxcr;
+ int div;
+ ulong fvco;
+
+ if (div_id > _DIV_NB)
+ return -EINVAL;
+
+ fvco = pll_get_fvco(priv, pll_id);
+
+ if (fvco <= clk_rate)
+ div = 1;
+ else
+ div = DIV_ROUND_UP(fvco, clk_rate);
+
+ if (div > 128)
+ div = 128;
+
+ debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
+ /* stop the requested output */
+ clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
+ /* change divider */
+ clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
+ RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
+ (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
+ /* start the requested output */
+ setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
+
+ return 0;
+}
+
+static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
+{
+ struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
+ int p;
+
+ switch (clk->id) {
+ case LTDC_PX:
+ case DSI_PX:
+ break;
+ default:
+ pr_err("not supported");
+ return -EINVAL;
+ }
+
+ p = stm32mp1_clk_get_parent(priv, clk->id);
+ if (p < 0)
+ return -EINVAL;
+
+ switch (p) {
+ case _PLL4_Q:
+ /* for LTDC_PX and DSI_PX case */
+ return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
+ }
+
+ return -EINVAL;
+}
+
static void stm32mp1_osc_clk_init(const char *name,
struct stm32mp1_clk_priv *priv,
int index)
.enable = stm32mp1_clk_enable,
.disable = stm32mp1_clk_disable,
.get_rate = stm32mp1_clk_get_rate,
-};
-
-static const struct udevice_id stm32mp1_clk_ids[] = {
- { .compatible = "st,stm32mp1-rcc-clk" },
- { }
+ .set_rate = stm32mp1_clk_set_rate,
};
U_BOOT_DRIVER(stm32mp1_clock) = {
.name = "stm32mp1_clk",
.id = UCLASS_CLK,
- .of_match = stm32mp1_clk_ids,
.ops = &stm32mp1_clk_ops,
.priv_auto_alloc_size = sizeof(struct stm32mp1_clk_priv),
.probe = stm32mp1_clk_probe,
projects / oweals / u-boot.git / blobdiff