#define RCC_FMCCKSELR 0x904
#define RCC_USBCKSELR 0x91C
#define RCC_DSICKSELR 0x924
+#define RCC_ADCCKSELR 0x928
#define RCC_MP_APB1ENSETR 0xA00
#define RCC_MP_APB2ENSETR 0XA08
#define RCC_MP_APB3ENSETR 0xA10
#define RCC_MP_AHB2ENSETR 0xA18
+#define RCC_MP_AHB3ENSETR 0xA20
#define RCC_MP_AHB4ENSETR 0xA28
/* used for most of SELR register */
#define RCC_BDCR_LSEON BIT(0)
#define RCC_BDCR_LSEBYP BIT(1)
#define RCC_BDCR_LSERDY BIT(2)
+#define RCC_BDCR_DIGBYP BIT(3)
#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
#define RCC_BDCR_LSEDRV_SHIFT 4
#define RCC_BDCR_LSECSSON BIT(8)
/* used for ALL PLLNCR registers */
#define RCC_PLLNCR_PLLON BIT(0)
#define RCC_PLLNCR_PLLRDY BIT(1)
+#define RCC_PLLNCR_SSCG_CTRL BIT(2)
#define RCC_PLLNCR_DIVPEN BIT(4)
#define RCC_PLLNCR_DIVQEN BIT(5)
#define RCC_PLLNCR_DIVREN BIT(6)
/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
#define RCC_OCENR_HSION BIT(0)
#define RCC_OCENR_CSION BIT(4)
+#define RCC_OCENR_DIGBYP BIT(7)
#define RCC_OCENR_HSEON BIT(8)
#define RCC_OCENR_HSEBYP BIT(10)
#define RCC_OCENR_HSECSSON BIT(11)
_LSI,
_LSE,
_I2S_CKIN,
- _USB_PHY_48,
NB_OSC,
/* other parent source */
_CK_MPU,
_CK_MCU,
_DSI_PHY,
+ _USB_PHY_48,
_PARENT_NB,
_UNKNOWN_ID = 0xff,
};
_USBO_SEL,
_STGEN_SEL,
_DSI_SEL,
+ _ADC12_SEL,
_PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff,
};
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
+ STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
+ STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
+
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
+static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
+ STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
};
#ifdef STM32MP1_CLOCK_TREE_INIT
1, 2, 3, 4, 4, 4, 4, 4
};
-#ifdef DEBUG
-static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
+static const __maybe_unused
+char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
[_HSI] = "HSI",
[_HSE] = "HSE",
[_CSI] = "CSI",
[_DSI_PHY] = "DSI_PHY_PLL",
};
-static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
+static const __maybe_unused
+char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
[_I2C12_SEL] = "I2C12",
[_I2C35_SEL] = "I2C35",
[_I2C46_SEL] = "I2C46",
[_USBO_SEL] = "USBO",
[_STGEN_SEL] = "STGEN",
[_DSI_SEL] = "DSI",
+ [_ADC12_SEL] = "ADC12",
};
-#endif
static const struct stm32mp1_clk_data stm32mp1_data = {
.gate = stm32mp1_clk_gate,
break;
/* other */
case _USB_PHY_48:
- clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48);
+ clock = 48000000;
break;
case _DSI_PHY:
{
static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
{
- if (enable)
- setbits_le32(rcc + RCC_OCENSETR, mask_on);
- else
- setbits_le32(rcc + RCC_OCENCLRR, mask_on);
+ writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
}
static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
return ret;
}
-static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv)
+static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
+ int lsedrv)
{
u32 value;
- if (bypass)
+ if (digbyp)
+ setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
+
+ if (bypass || digbyp)
setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
/*
stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
}
-static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int css)
+static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
{
- if (bypass)
- setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP);
+ if (digbyp)
+ writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
+ if (bypass || digbyp)
+ writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
if (css)
- setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON);
+ writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
}
static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
{
- stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION);
+ stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
}
{
const struct stm32mp1_clk_pll *pll = priv->data->pll;
- writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr);
+ clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
+ RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
+ RCC_PLLNCR_DIVREN,
+ RCC_PLLNCR_PLLON);
}
static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
RCC_PLLNCSGR_SSCG_MODE_MASK);
writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
+
+ setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
}
static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
rate = stm32mp1_clk_get(priv, p);
if (cntfid0 != rate) {
+ u64 counter;
+
pr_debug("System Generic Counter (STGEN) update\n");
clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
- writel(0x0, stgenc + STGENC_CNTCVL);
- writel(0x0, stgenc + STGENC_CNTCVU);
+ counter = (u64)readl(stgenc + STGENC_CNTCVL);
+ counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
+ counter = lldiv(counter * (u64)rate, cntfid0);
+ writel((u32)counter, stgenc + STGENC_CNTCVL);
+ writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
writel(rate, stgenc + STGENC_CNTFID0);
setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
stm32mp1_lsi_set(rcc, 1);
if (priv->osc[_LSE]) {
- int bypass;
- int lsedrv;
+ int bypass, digbyp, lsedrv;
struct udevice *dev = priv->osc_dev[_LSE];
bypass = dev_read_bool(dev, "st,bypass");
+ digbyp = dev_read_bool(dev, "st,digbypass");
lse_css = dev_read_bool(dev, "st,css");
lsedrv = dev_read_u32_default(dev, "st,drive",
LSEDRV_MEDIUM_HIGH);
- stm32mp1_lse_enable(rcc, bypass, lsedrv);
+ stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
}
if (priv->osc[_HSE]) {
- int bypass, css;
+ int bypass, digbyp, css;
struct udevice *dev = priv->osc_dev[_HSE];
bypass = dev_read_bool(dev, "st,bypass");
+ digbyp = dev_read_bool(dev, "st,digbypass");
css = dev_read_bool(dev, "st,css");
- stm32mp1_hse_enable(rcc, bypass, css);
+ stm32mp1_hse_enable(rcc, bypass, digbyp, css);
}
/* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
* => switch on CSI even if node is not present in device tree
[_HSE] = "clk-hse",
[_CSI] = "clk-csi",
[_I2S_CKIN] = "i2s_ckin",
- [_USB_PHY_48] = "ck_usbo_48m"};
+ };
for (i = 0; i < NB_OSC; i++) {
stm32mp1_osc_clk_init(name[i], priv, i);
}
}
+static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
+{
+ char buf[32];
+ int i, s, p;
+
+ printf("Clocks:\n");
+ for (i = 0; i < _PARENT_NB; i++) {
+ printf("- %s : %s MHz\n",
+ stm32mp1_clk_parent_name[i],
+ strmhz(buf, stm32mp1_clk_get(priv, i)));
+ }
+ printf("Source Clocks:\n");
+ for (i = 0; i < _PARENT_SEL_NB; i++) {
+ p = (readl(priv->base + priv->data->sel[i].offset) >>
+ priv->data->sel[i].src) & priv->data->sel[i].msk;
+ if (p < priv->data->sel[i].nb_parent) {
+ s = priv->data->sel[i].parent[p];
+ printf("- %s(%d) => parent %s(%d)\n",
+ stm32mp1_clk_parent_sel_name[i], i,
+ stm32mp1_clk_parent_name[s], s);
+ } else {
+ printf("- %s(%d) => parent index %d is invalid\n",
+ stm32mp1_clk_parent_sel_name[i], i, p);
+ }
+ }
+}
+
+#ifdef CONFIG_CMD_CLK
+int soc_clk_dump(void)
+{
+ struct udevice *dev;
+ struct stm32mp1_clk_priv *priv;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(stm32mp1_clock),
+ &dev);
+ if (ret)
+ return ret;
+
+ priv = dev_get_priv(dev);
+
+ stm32mp1_clk_dump(priv);
+
+ return 0;
+}
+#endif
+
static int stm32mp1_clk_probe(struct udevice *dev)
{
int result = 0;
result = stm32mp1_clktree(dev);
#endif
+#ifndef CONFIG_SPL_BUILD
+#if defined(DEBUG)
+ /* display debug information for probe after relocation */
+ if (gd->flags & GD_FLG_RELOC)
+ stm32mp1_clk_dump(priv);
+#endif
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+ if (gd->flags & GD_FLG_RELOC) {
+ char buf[32];
+
+ printf("Clocks:\n");
+ printf("- MPU : %s MHz\n",
+ strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU)));
+ printf("- MCU : %s MHz\n",
+ strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
+ printf("- AXI : %s MHz\n",
+ strmhz(buf, stm32mp1_clk_get(priv, _ACLK)));
+ printf("- PER : %s MHz\n",
+ strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
+ /* DDRPHYC father */
+ printf("- DDR : %s MHz\n",
+ strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R)));
+ }
+#endif /* CONFIG_DISPLAY_CPUINFO */
+#endif
+
return result;
}
projects / oweals / u-boot.git / blobdiff