projects / oweals / u-boot.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
Merge tag 'efi-2020-07-rc2-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
[oweals/u-boot.git] / drivers / clk / clk_stm32mp1.c
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 5806d48696f45061b600c5e648f3468953d2d946..50df8425bf763b85d6200693a9094dc44e72f7c8 100644 (file)
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -10,12 +10,16 @@
 #include <regmap.h>
 #include <spl.h>
 #include <syscon.h>
+#include <time.h>
+#include <vsprintf.h>
 #include <linux/io.h>
 #include <linux/iopoll.h>
 #include <dt-bindings/clock/stm32mp1-clks.h>
 #include <dt-bindings/clock/stm32mp1-clksrc.h>
 
-#ifndef CONFIG_STM32MP1_TRUSTED
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_TFABOOT
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 /* activate clock tree initialization in the driver */
 #define STM32MP1_CLOCK_TREE_INIT
@@ -91,6 +95,7 @@
 #define RCC_I2C12CKSELR                0x8C0
 #define RCC_I2C35CKSELR                0x8C4
 #define RCC_SPI2S1CKSELR       0x8D8
+#define RCC_SPI45CKSELR                0x8E0
 #define RCC_UART6CKSELR                0x8E4
 #define RCC_UART24CKSELR       0x8E8
 #define RCC_UART35CKSELR       0x8EC
@@ -300,6 +305,7 @@ enum stm32mp1_parent_sel {
        _DSI_SEL,
        _ADC12_SEL,
        _SPI1_SEL,
+       _SPI45_SEL,
        _RTC_SEL,
        _PARENT_SEL_NB,
        _UNKNOWN_SEL = 0xff,
@@ -523,6 +529,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
        STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 
        STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
        STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 
        STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
@@ -559,6 +566,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
        STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 
        STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
 
        STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
        STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
@@ -598,6 +606,8 @@ static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
                                 _PLL3_R};
+static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
+                                  _HSE_KER};
 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
 
 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
@@ -616,14 +626,15 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
        STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
                            sdmmc3_parents),
        STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
-       STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
-       STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
+       STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
+       STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
        STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
        STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
        STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
        STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
-       STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
+       STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
        STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
+       STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
        STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
                            (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
                            rtc_parents),
@@ -742,6 +753,7 @@ char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
        [_DSI_SEL] = "DSI",
        [_ADC12_SEL] = "ADC12",
        [_SPI1_SEL] = "SPI1",
+       [_SPI45_SEL] = "SPI45",
        [_RTC_SEL] = "RTC",
 };
 
@@ -759,9 +771,6 @@ static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
                return 0;
        }
 
-       debug("%s: clk id %d = %x : %ld kHz\n", __func__, idx,
-             (u32)priv->osc[idx], priv->osc[idx] / 1000);
-
        return priv->osc[idx];
 }
 
@@ -863,8 +872,6 @@ static ulong  pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
        src = selr & RCC_SELR_SRC_MASK;
 
        refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
-       debug("PLL%d : selr=%x refclk = %d kHz\n",
-             pll_id, selr, (u32)(refclk / 1000));
 
        return refclk;
 }
@@ -889,9 +896,6 @@ static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
        divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
        divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
 
-       debug("PLL%d : cfgr1=%x fracr=%x DIVN=%d DIVM=%d\n",
-             pll_id, cfgr1, fracr, divn, divm);
-
        refclk = pll_get_fref_ck(priv, pll_id);
 
        /* with FRACV :
@@ -908,7 +912,6 @@ static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
        } else {
                fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
        }
-       debug("PLL%d : %s = %ld\n", pll_id, __func__, fvco);
 
        return fvco;
 }
@@ -921,17 +924,13 @@ static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
        ulong dfout;
        u32 cfgr2;
 
-       debug("%s(%d, %d)\n", __func__, pll_id, div_id);
        if (div_id >= _DIV_NB)
                return 0;
 
        cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
        divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
 
-       debug("PLL%d : cfgr2=%x DIVY=%d\n", pll_id, cfgr2, divy);
-
        dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
-       debug("        => dfout = %d kHz\n", (u32)(dfout / 1000));
 
        return dfout;
 }
@@ -1226,7 +1225,7 @@ static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
 }
 
 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
-                               int lsedrv)
+                               u32 lsedrv)
 {
        u32 value;
 
@@ -1574,9 +1573,6 @@ static void stgen_config(struct stm32mp1_clk_priv *priv)
 
                /* need to update gd->arch.timer_rate_hz with new frequency */
                timer_init();
-               pr_debug("gd->arch.timer_rate_hz = %x\n",
-                        (u32)gd->arch.timer_rate_hz);
-               pr_debug("Tick = %x\n", (u32)(get_ticks()));
        }
 }
 
@@ -1662,8 +1658,8 @@ static int stm32mp1_clktree(struct udevice *dev)
        unsigned int clkdiv[CLKDIV_NB];
        unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
        ofnode plloff[_PLL_NB];
-       int ret;
-       int i, len;
+       int ret, len;
+       uint i;
        int lse_css = 0;
        const u32 *pkcs_cell;
 
@@ -1709,7 +1705,8 @@ static int stm32mp1_clktree(struct udevice *dev)
                stm32mp1_lsi_set(rcc, 1);
 
        if (priv->osc[_LSE]) {
-               int bypass, digbyp, lsedrv;
+               int bypass, digbyp;
+               u32 lsedrv;
                struct udevice *dev = priv->osc_dev[_LSE];
 
                bypass = dev_read_bool(dev, "st,bypass");
@@ -1882,7 +1879,6 @@ static int pll_set_output_rate(struct udevice *dev,
        if (div > 128)
                div = 128;
 
-       debug("fvco = %ld, clk_rate = %ld, div=%d\n", fvco, clk_rate, div);
        /* stop the requested output */
        clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
        /* change divider */
@@ -1915,6 +1911,9 @@ static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
        }
 
        p = stm32mp1_clk_get_parent(priv, clk->id);
+#ifdef DEBUG
+       debug("%s: parent = %d:%s\n", __func__, p, stm32mp1_clk_parent_name[p]);
+#endif
        if (p < 0)
                return -EINVAL;
 
@@ -1932,6 +1931,7 @@ static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
                return result;
        }
 #endif
+
        case _PLL4_Q:
                /* for LTDC_PX and DSI_PX case */
                return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
@@ -2055,22 +2055,22 @@ static int stm32mp1_clk_probe(struct udevice *dev)
                stm32mp1_clk_dump(priv);
 #endif
 
+       gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
+       gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
+       /* DDRPHYC father */
+       gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
 #if defined(CONFIG_DISPLAY_CPUINFO)
        if (gd->flags & GD_FLG_RELOC) {
                char buf[32];
 
                printf("Clocks:\n");
-               printf("- MPU : %s MHz\n",
-                      strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU)));
+               printf("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
                printf("- MCU : %s MHz\n",
                       strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
-               printf("- AXI : %s MHz\n",
-                      strmhz(buf, stm32mp1_clk_get(priv, _ACLK)));
+               printf("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
                printf("- PER : %s MHz\n",
                       strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
-               /* DDRPHYC father */
-               printf("- DDR : %s MHz\n",
-                      strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R)));
+               printf("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
        }
 #endif /* CONFIG_DISPLAY_CPUINFO */
 #endif
Unnamed repository; edit this file 'description' to name the repository.