Merge tag 'efi-2020-07-rc2-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

[oweals/u-boot.git] / drivers / clk / clk_stm32mp1.c

diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 3718970dc7c4d2754a936e2b7f9567d6ba3b1fcc..50df8425bf763b85d6200693a9094dc44e72f7c8 100644 (file)
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -19,7 +19,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_STM32MP1_TRUSTED
+#ifndef CONFIG_TFABOOT
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 /* activate clock tree initialization in the driver */
 #define STM32MP1_CLOCK_TREE_INIT
@@ -95,6 +95,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define RCC_I2C12CKSELR                0x8C0
 #define RCC_I2C35CKSELR                0x8C4
 #define RCC_SPI2S1CKSELR       0x8D8
+#define RCC_SPI45CKSELR                0x8E0
 #define RCC_UART6CKSELR                0x8E4
 #define RCC_UART24CKSELR       0x8E8
 #define RCC_UART35CKSELR       0x8EC
@@ -304,6 +305,7 @@ enum stm32mp1_parent_sel {
        _DSI_SEL,
        _ADC12_SEL,
        _SPI1_SEL,
+       _SPI45_SEL,
        _RTC_SEL,
        _PARENT_SEL_NB,
        _UNKNOWN_SEL = 0xff,
@@ -527,6 +529,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
        STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
 
        STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
        STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 
        STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
@@ -563,6 +566,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
        STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 
        STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
+       STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
 
        STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
        STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
@@ -602,6 +606,8 @@ static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
 static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
 static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
                                 _PLL3_R};
+static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
+                                  _HSE_KER};
 static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
 
 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
@@ -620,14 +626,15 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
        STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
                            sdmmc3_parents),
        STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
-       STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents),
-       STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents),
+       STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
+       STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
        STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
        STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
        STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
        STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
-       STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x1, adc_parents),
+       STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
        STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
+       STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
        STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
                            (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
                            rtc_parents),
@@ -746,6 +753,7 @@ char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
        [_DSI_SEL] = "DSI",
        [_ADC12_SEL] = "ADC12",
        [_SPI1_SEL] = "SPI1",
+       [_SPI45_SEL] = "SPI45",
        [_RTC_SEL] = "RTC",
 };
 
@@ -1217,7 +1225,7 @@ static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
 }
 
 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
-                               int lsedrv)
+                               u32 lsedrv)
 {
        u32 value;
 
@@ -1650,8 +1658,8 @@ static int stm32mp1_clktree(struct udevice *dev)
        unsigned int clkdiv[CLKDIV_NB];
        unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
        ofnode plloff[_PLL_NB];
-       int ret;
-       int i, len;
+       int ret, len;
+       uint i;
        int lse_css = 0;
        const u32 *pkcs_cell;
 
@@ -1697,7 +1705,8 @@ static int stm32mp1_clktree(struct udevice *dev)
                stm32mp1_lsi_set(rcc, 1);
 
        if (priv->osc[_LSE]) {
-               int bypass, digbyp, lsedrv;
+               int bypass, digbyp;
+               u32 lsedrv;
                struct udevice *dev = priv->osc_dev[_LSE];
 
                bypass = dev_read_bool(dev, "st,bypass");