Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell

[oweals/u-boot.git] / drivers / clk / clk_stm32h7.c

diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c
index 92db71431e45791cac86f83c1c43f7a0d9c10d2d..18d06b333dbe3d0b1e3a37ebfc0ecd0158a90d8a 100644 (file)
--- a/drivers/clk/clk_stm32h7.c
+++ b/drivers/clk/clk_stm32h7.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -15,8 +14,6 @@
 
 #include <dt-bindings/clock/stm32h7-clks.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 /* RCC CR specific definitions */
 #define RCC_CR_HSION                   BIT(0)
 #define RCC_CR_HSIRDY                  BIT(2)
@@ -635,7 +632,7 @@ static ulong stm32_clk_get_rate(struct clk *clk)
        struct stm32_rcc_regs *regs = priv->rcc_base;
        ulong sysclk = 0;
        u32 gate_offset;
-       u32 d1cfgr;
+       u32 d1cfgr, d3cfgr;
        /* prescaler table lookups for clock computation */
        u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
        u8 source, idx;
@@ -712,9 +709,10 @@ static ulong stm32_clk_get_rate(struct clk *clk)
                break;
 
        case RCC_APB4ENR:
-               if (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
+               d3cfgr = readl(&regs->d3cfgr);
+               if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
                        /* get D3 domain APB4 prescaler */
-                       idx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
+                       idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
                              RCC_D3CFGR_D3PPRE_SHIFT;
                        sysclk = sysclk / prescaler_table[idx];
                }