clk: armada-37xx-periph: fix DDR PHY clock divider values
[oweals/u-boot.git] / drivers / clk / clk_sandbox_ccf.c
index e126f18d8e96256f90914e0d0aaa548e849767db..3543bea70d2b32f5b21920d57b2103a76e22377d 100644 (file)
@@ -9,10 +9,13 @@
 #include <common.h>
 #include <dm.h>
 #include <clk.h>
+#include <malloc.h>
 #include <asm/clk.h>
 #include <clk-uclass.h>
+#include <dm/devres.h>
 #include <linux/clk-provider.h>
 #include <sandbox-clk.h>
+#include <linux/err.h>
 
 /*
  * Sandbox implementation of CCF primitives necessary for clk-uclass testing
@@ -25,6 +28,18 @@ struct clk_pllv3 {
        u32             div_shift;
 };
 
+int sandbox_clk_enable_count(struct clk *clk)
+{
+       struct clk *clkp = NULL;
+       int ret;
+
+       ret = clk_get_by_id(clk->id, &clkp);
+       if (ret)
+               return 0;
+
+       return clkp->enable_count;
+}
+
 static ulong clk_pllv3_get_rate(struct clk *clk)
 {
        unsigned long parent_rate = clk_get_parent_rate(clk);
@@ -254,6 +269,9 @@ static int sandbox_clk_ccf_probe(struct udevice *dev)
               sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
                                     &reg, 0));
 
+       clk_dm(SANDBOX_CLK_I2C_ROOT,
+              sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
+
        return 0;
 }