return 1;
}
+#ifdef CONFIG_SUNXI_AHCI
+/* The sunxi AHCI controller requires this undocumented setup */
+static void sunxi_dma_init(volatile u8 *port_mmio)
+{
+ clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
+}
+#endif
+
+int ahci_reset(u32 base)
+{
+ int i = 1000;
+ u32 host_ctl_reg = base + HOST_CTL;
+ u32 tmp = readl(host_ctl_reg); /* global controller reset */
+
+ if ((tmp & HOST_RESET) == 0)
+ writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
+
+ /*
+ * reset must complete within 1 second, or
+ * the hardware should be considered fried.
+ */
+ do {
+ udelay(1000);
+ tmp = readl(host_ctl_reg);
+ i--;
+ } while ((i > 0) && (tmp & HOST_RESET));
+
+ if (i == 0) {
+ printf("controller reset failed (0x%x)\n", tmp);
+ return -1;
+ }
+
+ return 0;
+}
+
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
cap_save &= ((1 << 28) | (1 << 17));
cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
- /* global controller reset */
- tmp = readl(mmio + HOST_CTL);
- if ((tmp & HOST_RESET) == 0)
- writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
-
- /* reset must complete within 1 second, or
- * the hardware should be considered fried.
- */
- i = 1000;
- do {
- udelay(1000);
- tmp = readl(mmio + HOST_CTL);
- if (!i--) {
- debug("controller reset failed (0x%x)\n", tmp);
- return -1;
- }
- } while (tmp & HOST_RESET);
+ ret = ahci_reset(probe_ent->mmio_base);
+ if (ret)
+ return ret;
writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
writel(cap_save, mmio + HOST_CAP);
msleep(500);
}
+#ifdef CONFIG_SUNXI_AHCI
+ sunxi_dma_init(port_mmio);
+#endif
+
/* Add the spinup command to whatever mode bits may
* already be on in the command register.
*/
cmd = readl(port_mmio + PORT_CMD);
- cmd |= PORT_CMD_FIS_RX;
cmd |= PORT_CMD_SPIN_UP;
writel_with_flush(cmd, port_mmio + PORT_CMD);
}
#endif
+static int wait_spinup(volatile u8 *port_mmio)
+{
+ ulong start;
+ u32 tf_data;
+
+ start = get_timer(0);
+ do {
+ tf_data = readl(port_mmio + PORT_TFDATA);
+ if (!(tf_data & ATA_BUSY))
+ return 0;
+ } while (get_timer(start) < WAIT_MS_SPINUP);
+
+ return -ETIMEDOUT;
+}
static int ahci_port_start(u8 port)
{
writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+#ifdef CONFIG_SUNXI_AHCI
+ sunxi_dma_init(port_mmio);
+#endif
+
writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
PORT_CMD_START, port_mmio + PORT_CMD);
debug("Exit start port %d\n", port);
- return 0;
+ /*
+ * Make sure interface is not busy based on error and status
+ * information from task file data register before proceeding
+ */
+ return wait_spinup(port_mmio);
}
u16 now_blocks; /* number of blocks per iteration */
u32 transfer_size; /* number of bytes per iteration */
- now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
+ now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
transfer_size = ATA_SECT_SIZE * now_blocks;
if (transfer_size > user_buffer_size) {
}
-void scsi_bus_reset(void)
+__weak void scsi_bus_reset(void)
{
/*Not implement*/
}
-
void scsi_print_error(ccb * pccb)
{
/*The ahci error info can be read in the ahci driver*/