/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
* Author: Jason Jin<Jason.jin@freescale.com>
* Zhang Wei<wei.zhang@freescale.com>
*
#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
+/*
+ * Some controllers limit number of blocks they can read/write at once.
+ * Contemporary SSD devices work much faster if the read/write size is aligned
+ * to a power of 2. Let's set default to 128 and allowing to be overwritten if
+ * needed.
+ */
+#ifndef MAX_SATA_BLOCKS_READ_WRITE
+#define MAX_SATA_BLOCKS_READ_WRITE 0x80
+#endif
static inline u32 ahci_port_base(u32 base, u32 port)
{
#define msleep(a) udelay(a * 1000)
-#define ssleep(a) msleep(a * 1000)
static int waiting_for_cmd_completed(volatile u8 *offset,
int timeout_msec,
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
+#ifndef CONFIG_SCSI_AHCI_PLAT
pci_dev_t pdev = probe_ent->dev;
+ u16 tmp16;
+ unsigned short vendor;
+#endif
volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
u32 tmp, cap_save;
- u16 tmp16;
int i, j;
volatile u8 *port_mmio;
- unsigned short vendor;
+
+ debug("ahci_host_init: start\n");
cap_save = readl(mmio + HOST_CAP);
cap_save &= ((1 << 28) | (1 << 17));
/* reset must complete within 1 second, or
* the hardware should be considered fried.
*/
- ssleep(1);
-
- tmp = readl(mmio + HOST_CTL);
- if (tmp & HOST_RESET) {
- debug("controller reset failed (0x%x)\n", tmp);
- return -1;
- }
+ i = 1000;
+ do {
+ udelay(1000);
+ tmp = readl(mmio + HOST_CTL);
+ if (!i--) {
+ debug("controller reset failed (0x%x)\n", tmp);
+ return -1;
+ }
+ } while (tmp & HOST_RESET);
writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
writel(cap_save, mmio + HOST_CAP);
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
+#ifndef CONFIG_SCSI_AHCI_PLAT
pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
if (vendor == PCI_VENDOR_ID_INTEL) {
tmp16 |= 0xf;
pci_write_config_word(pdev, 0x92, tmp16);
}
-
+#endif
probe_ent->cap = readl(mmio + HOST_CAP);
probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
debug("cap 0x%x port_map 0x%x n_ports %d\n",
probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
+ if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
+ probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
+
for (i = 0; i < probe_ent->n_ports; i++) {
probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
port_mmio = (u8 *) probe_ent->port[i].port_mmio;
tmp = readl(port_mmio + PORT_CMD);
if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
PORT_CMD_FIS_RX | PORT_CMD_START)) {
+ debug("Port %d is active. Deactivating.\n", i);
tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
PORT_CMD_FIS_RX | PORT_CMD_START);
writel_with_flush(tmp, port_mmio + PORT_CMD);
msleep(500);
}
+ debug("Spinning up port %d... ", i);
writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
j = 0;
- while (j < 100) {
- msleep(10);
+ while (j < 1000) {
tmp = readl(port_mmio + PORT_SCR_STAT);
if ((tmp & 0xf) == 0x3)
break;
+ udelay(1000);
j++;
}
+ if (j == 1000)
+ debug("timeout.\n");
+ else
+ debug("ok.\n");
tmp = readl(port_mmio + PORT_SCR_ERR);
debug("PORT_SCR_ERR 0x%x\n", tmp);
/* set irq mask (enables interrupts) */
writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
- /*register linkup ports */
+ /* register linkup ports */
tmp = readl(port_mmio + PORT_SCR_STAT);
debug("Port %d status: 0x%x\n", i, tmp);
if ((tmp & 0xf) == 0x03)
writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
tmp = readl(mmio + HOST_CTL);
debug("HOST_CTL 0x%x\n", tmp);
-
+#ifndef CONFIG_SCSI_AHCI_PLAT
pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
tmp |= PCI_COMMAND_MASTER;
pci_write_config_word(pdev, PCI_COMMAND, tmp16);
-
+#endif
return 0;
}
static void ahci_print_info(struct ahci_probe_ent *probe_ent)
{
+#ifndef CONFIG_SCSI_AHCI_PLAT
pci_dev_t pdev = probe_ent->dev;
+ u16 cc;
+#endif
volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
- u32 vers, cap, impl, speed;
+ u32 vers, cap, cap2, impl, speed;
const char *speed_s;
- u16 cc;
const char *scc_s;
vers = readl(mmio + HOST_VERSION);
cap = probe_ent->cap;
+ cap2 = readl(mmio + HOST_CAP2);
impl = probe_ent->port_map;
speed = (cap >> 20) & 0xf;
speed_s = "1.5";
else if (speed == 2)
speed_s = "3";
+ else if (speed == 3)
+ speed_s = "6";
else
speed_s = "?";
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ scc_s = "SATA";
+#else
pci_read_config_word(pdev, 0x0a, &cc);
if (cc == 0x0101)
scc_s = "IDE";
scc_s = "RAID";
else
scc_s = "unknown";
-
+#endif
printf("AHCI %02x%02x.%02x%02x "
"%u slots %u ports %s Gbps 0x%x impl %s mode\n",
(vers >> 24) & 0xff,
((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
printf("flags: "
- "%s%s%s%s%s%s"
- "%s%s%s%s%s%s%s\n",
+ "%s%s%s%s%s%s%s"
+ "%s%s%s%s%s%s%s"
+ "%s%s%s%s%s%s\n",
cap & (1 << 31) ? "64bit " : "",
cap & (1 << 30) ? "ncq " : "",
cap & (1 << 28) ? "ilck " : "",
cap & (1 << 19) ? "nz " : "",
cap & (1 << 18) ? "only " : "",
cap & (1 << 17) ? "pmp " : "",
+ cap & (1 << 16) ? "fbss " : "",
cap & (1 << 15) ? "pio " : "",
cap & (1 << 14) ? "slum " : "",
- cap & (1 << 13) ? "part " : "");
+ cap & (1 << 13) ? "part " : "",
+ cap & (1 << 7) ? "ccc " : "",
+ cap & (1 << 6) ? "ems " : "",
+ cap & (1 << 5) ? "sxs " : "",
+ cap2 & (1 << 2) ? "apst " : "",
+ cap2 & (1 << 1) ? "nvmp " : "",
+ cap2 & (1 << 0) ? "boh " : "");
}
+#ifndef CONFIG_SCSI_AHCI_PLAT
static int ahci_init_one(pci_dev_t pdev)
{
- u32 iobase;
u16 vendor;
int rc;
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
probe_ent->dev = pdev;
- pci_read_config_dword(pdev, AHCI_PCI_BAR, &iobase);
- iobase &= ~0xf;
-
probe_ent->host_flags = ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
| ATA_FLAG_MMIO
probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
- probe_ent->mmio_base = iobase;
+ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
+ debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
/* Take from kernel:
* JMicron-specific fixup:
err_out:
return rc;
}
-
+#endif
#define MAX_DATA_BYTE_COUNT (4*1024*1024)
}
+#ifdef CONFIG_AHCI_SETFEATURES_XFER
static void ahci_set_feature(u8 port)
{
struct ahci_ioports *pp = &(probe_ent->port[port]);
u32 cmd_fis_len = 5; /* five dwords */
u8 fis[20];
- /*set feature */
+ /* set feature */
memset(fis, 0, 20);
fis[0] = 0x27;
fis[1] = 1 << 7;
readl(port_mmio + PORT_CMD_ISSUE);
if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
- printf("set feature error!\n");
+ printf("set feature error on port %d!\n", port);
}
}
+#endif
static int ahci_port_start(u8 port)
* 32 bytes each in size
*/
pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
- debug("cmd_slot = 0x%x\n", pp->cmd_slot);
+ debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
mem += (AHCI_CMD_SLOT_SZ + 224);
/*
}
-static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
- int buf_len)
+static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
+ int buf_len, u8 is_write)
{
struct ahci_ioports *pp = &(probe_ent->port[port]);
u32 port_status;
int sg_count;
- debug("Enter get_ahci_device_data: for port %d\n", port);
+ debug("Enter %s: for port %d\n", __func__, port);
if (port > probe_ent->n_ports) {
printf("Invaild port number %d\n", port);
memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
sg_count = ahci_fill_sg(port, buf, buf_len);
- opts = (fis_len >> 2) | (sg_count << 16);
+ opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
ahci_fill_cmd_slot(pp, opts);
writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
printf("timeout exit!\n");
return -1;
}
- debug("get_ahci_device_data: %d byte transferred.\n",
- pp->cmd_slot->status);
+ debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
return 0;
}
{
int i;
for (i = 0; i < len / 2; i++)
- target[i] = le16_to_cpu(src[i]);
+ target[i] = swab16(src[i]);
return (char *)target;
}
if (!(tmpid = malloc(sizeof(hd_driveid_t))))
return -ENOMEM;
- if (get_ahci_device_data(port, (u8 *) & fis, 20,
- tmpid, sizeof(hd_driveid_t))) {
+ if (ahci_device_data_io(port, (u8 *) &fis, 20, tmpid,
+ sizeof(hd_driveid_t), 0)) {
debug("scsi_ahci: SCSI inquiry command failure.\n");
return -EIO;
}
/*
- * SCSI READ10 command operation.
+ * SCSI READ10/WRITE10 command operation.
*/
-static int ata_scsiop_read10(ccb * pccb)
+static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
{
- u64 lba = 0;
- u32 len = 0;
+ u32 lba = 0;
+ u16 blocks = 0;
u8 fis[20];
+ u8 *user_buffer = pccb->pdata;
+ u32 user_buffer_size = pccb->datalen;
- lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
- | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
- len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
+ /* Retrieve the base LBA number from the ccb structure. */
+ memcpy(&lba, pccb->cmd + 2, sizeof(lba));
+ lba = be32_to_cpu(lba);
- /* For 10-byte and 16-byte SCSI R/W commands, transfer
+ /*
+ * And the number of blocks.
+ *
+ * For 10-byte and 16-byte SCSI R/W commands, transfer
* length 0 means transfer 0 block of data.
* However, for ATA R/W commands, sector count 0 means
* 256 or 65536 sectors, not 0 sectors as in SCSI.
*
* WARNING: one or two older ATA drives treat 0 as 0...
*/
- if (!len)
- return 0;
+ blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
+
+ debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
+ is_write ? "write" : "read", (unsigned)lba, blocks);
+
+ /* Preset the FIS */
memset(fis, 0, 20);
+ fis[0] = 0x27; /* Host to device FIS. */
+ fis[1] = 1 << 7; /* Command FIS. */
+ /* Command byte (read/write). */
+ fis[2] = is_write ? ATA_CMD_WR_DMA : ATA_CMD_RD_DMA;
- /* Construct the FIS */
- fis[0] = 0x27; /* Host to device FIS. */
- fis[1] = 1 << 7; /* Command FIS. */
- fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
-
- /* LBA address, only support LBA28 in this driver */
- fis[4] = pccb->cmd[5];
- fis[5] = pccb->cmd[4];
- fis[6] = pccb->cmd[3];
- fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
-
- /* Sector Count */
- fis[12] = pccb->cmd[8];
- fis[13] = pccb->cmd[7];
-
- /* Read from ahci */
- if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
- pccb->pdata, pccb->datalen)) {
- debug("scsi_ahci: SCSI READ10 command failure.\n");
- return -EIO;
+ while (blocks) {
+ u16 now_blocks; /* number of blocks per iteration */
+ u32 transfer_size; /* number of bytes per iteration */
+
+ now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
+
+ transfer_size = ATA_BLOCKSIZE * now_blocks;
+ if (transfer_size > user_buffer_size) {
+ printf("scsi_ahci: Error: buffer too small.\n");
+ return -EIO;
+ }
+
+ /* LBA address, only support LBA28 in this driver */
+ fis[4] = (lba >> 0) & 0xff;
+ fis[5] = (lba >> 8) & 0xff;
+ fis[6] = (lba >> 16) & 0xff;
+ fis[7] = ((lba >> 24) & 0xf) | 0xe0;
+
+ /* Block (sector) count */
+ fis[12] = (now_blocks >> 0) & 0xff;
+ fis[13] = (now_blocks >> 8) & 0xff;
+
+ /* Read/Write from ahci */
+ if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
+ user_buffer, user_buffer_size,
+ is_write)) {
+ debug("scsi_ahci: SCSI %s10 command failure.\n",
+ is_write ? "WRITE" : "READ");
+ return -EIO;
+ }
+ user_buffer += transfer_size;
+ user_buffer_size -= transfer_size;
+ blocks -= now_blocks;
+ lba += now_blocks;
}
return 0;
*/
static int ata_scsiop_read_capacity10(ccb *pccb)
{
- u8 buf[8];
+ u32 cap;
+ u32 block_size;
if (!ataid[pccb->target]) {
printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
return -EPERM;
}
- memset(buf, 0, 8);
+ cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
+ if (cap == 0xfffffff) {
+ unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;
+ if (cap48[2] || cap48[3]) {
+ cap = 0xffffffff;
+ } else {
+ cap = (le16_to_cpu(cap48[1]) << 16) |
+ (le16_to_cpu(cap48[0]));
+ }
+ }
+
+ cap = cpu_to_be32(cap);
+ memcpy(pccb->pdata, &cap, sizeof(cap));
- *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity);
+ block_size = cpu_to_be32((u32)512);
+ memcpy(&pccb->pdata[4], &block_size, 4);
- buf[6] = 512 >> 8;
- buf[7] = 512 & 0xff;
+ return 0;
+}
- memcpy(pccb->pdata, buf, 8);
+
+/*
+ * SCSI READ CAPACITY16 command operation.
+ */
+static int ata_scsiop_read_capacity16(ccb *pccb)
+{
+ u64 cap;
+ u64 block_size;
+
+ if (!ataid[pccb->target]) {
+ printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
+ "\tNo ATA info!\n"
+ "\tPlease run SCSI commmand INQUIRY firstly!\n");
+ return -EPERM;
+ }
+
+ cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
+ if (cap == 0xfffffff) {
+ memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));
+ cap = le64_to_cpu(cap);
+ }
+
+ cap = cpu_to_be64(cap);
+ memcpy(pccb->pdata, &cap, sizeof(cap));
+
+ block_size = cpu_to_be64((u64)512);
+ memcpy(&pccb->pdata[8], &block_size, 8);
return 0;
}
switch (pccb->cmd[0]) {
case SCSI_READ10:
- ret = ata_scsiop_read10(pccb);
+ ret = ata_scsiop_read_write(pccb, 0);
+ break;
+ case SCSI_WRITE10:
+ ret = ata_scsiop_read_write(pccb, 1);
break;
- case SCSI_RD_CAPAC:
+ case SCSI_RD_CAPAC10:
ret = ata_scsiop_read_capacity10(pccb);
break;
+ case SCSI_RD_CAPAC16:
+ ret = ata_scsiop_read_capacity16(pccb);
+ break;
case SCSI_TST_U_RDY:
ret = ata_scsiop_test_unit_ready(pccb);
break;
int i;
u32 linkmap;
+#ifndef CONFIG_SCSI_AHCI_PLAT
ahci_init_one(busdevfunc);
+#endif
linkmap = probe_ent->link_port_map;
- for (i = 0; i < CFG_SCSI_MAX_SCSI_ID; i++) {
+ for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
if (((linkmap >> i) & 0x01)) {
if (ahci_port_start((u8) i)) {
printf("Can not start port %d\n", i);
continue;
}
+#ifdef CONFIG_AHCI_SETFEATURES_XFER
ahci_set_feature((u8) i);
+#endif
}
}
}
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int ahci_init(u32 base)
+{
+ int i, rc = 0;
+ u32 linkmap;
+
+ memset(ataid, 0, sizeof(ataid));
+
+ probe_ent = malloc(sizeof(struct ahci_probe_ent));
+ memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
+
+ probe_ent->host_flags = ATA_FLAG_SATA
+ | ATA_FLAG_NO_LEGACY
+ | ATA_FLAG_MMIO
+ | ATA_FLAG_PIO_DMA
+ | ATA_FLAG_NO_ATAPI;
+ probe_ent->pio_mask = 0x1f;
+ probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
+
+ probe_ent->mmio_base = base;
+
+ /* initialize adapter */
+ rc = ahci_host_init(probe_ent);
+ if (rc)
+ goto err_out;
+
+ ahci_print_info(probe_ent);
+
+ linkmap = probe_ent->link_port_map;
+
+ for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
+ if (((linkmap >> i) & 0x01)) {
+ if (ahci_port_start((u8) i)) {
+ printf("Can not start port %d\n", i);
+ continue;
+ }
+#ifdef CONFIG_AHCI_SETFEATURES_XFER
+ ahci_set_feature((u8) i);
+#endif
+ }
+ }
+err_out:
+ return rc;
+}
+#endif
void scsi_bus_reset(void)
{