/* Maximum timeouts for each event */
#define WAIT_MS_SPINUP 20000
-#define WAIT_MS_DATAIO 5000
+#define WAIT_MS_DATAIO 10000
#define WAIT_MS_FLUSH 5000
#define WAIT_MS_LINKUP 200
-static inline u32 ahci_port_base(u32 base, u32 port)
+static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
{
return base + 0x100 + (port * 0x80);
}
-static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
+static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
unsigned int port_idx)
{
base = ahci_port_base(base, port_idx);
#define msleep(a) udelay(a * 1000)
-static void ahci_dcache_flush_range(unsigned begin, unsigned len)
+static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
{
const unsigned long start = begin;
const unsigned long end = start + len;
* controller is invalidated from dcache; next access comes from
* physical RAM.
*/
-static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
+static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
{
const unsigned long start = begin;
const unsigned long end = start + len;
AHCI_PORT_PRIV_DMA_SZ);
}
-static int waiting_for_cmd_completed(volatile u8 *offset,
+static int waiting_for_cmd_completed(void __iomem *offset,
int timeout_msec,
u32 sign)
{
{
u32 tmp;
int j = 0;
- u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
+ void __iomem *port_mmio = probe_ent->port[port].port_mmio;
/*
* Bring up SATA link.
#ifdef CONFIG_SUNXI_AHCI
/* The sunxi AHCI controller requires this undocumented setup */
-static void sunxi_dma_init(volatile u8 *port_mmio)
+static void sunxi_dma_init(void __iomem *port_mmio)
{
clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
}
#endif
+int ahci_reset(void __iomem *base)
+{
+ int i = 1000;
+ u32 __iomem *host_ctl_reg = base + HOST_CTL;
+ u32 tmp = readl(host_ctl_reg); /* global controller reset */
+
+ if ((tmp & HOST_RESET) == 0)
+ writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
+
+ /*
+ * reset must complete within 1 second, or
+ * the hardware should be considered fried.
+ */
+ do {
+ udelay(1000);
+ tmp = readl(host_ctl_reg);
+ i--;
+ } while ((i > 0) && (tmp & HOST_RESET));
+
+ if (i == 0) {
+ printf("controller reset failed (0x%x)\n", tmp);
+ return -1;
+ }
+
+ return 0;
+}
+
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
u16 tmp16;
unsigned short vendor;
#endif
- volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
+ void __iomem *mmio = probe_ent->mmio_base;
u32 tmp, cap_save, cmd;
int i, j, ret;
- volatile u8 *port_mmio;
+ void __iomem *port_mmio;
u32 port_map;
debug("ahci_host_init: start\n");
cap_save &= ((1 << 28) | (1 << 17));
cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
- /* global controller reset */
- tmp = readl(mmio + HOST_CTL);
- if ((tmp & HOST_RESET) == 0)
- writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
-
- /* reset must complete within 1 second, or
- * the hardware should be considered fried.
- */
- i = 1000;
- do {
- udelay(1000);
- tmp = readl(mmio + HOST_CTL);
- if (!i--) {
- debug("controller reset failed (0x%x)\n", tmp);
- return -1;
- }
- } while (tmp & HOST_RESET);
+ ret = ahci_reset(probe_ent->mmio_base);
+ if (ret)
+ return ret;
writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
writel(cap_save, mmio + HOST_CAP);
for (i = 0; i < probe_ent->n_ports; i++) {
if (!(port_map & (1 << i)))
continue;
- probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
+ probe_ent->port[i].port_mmio = ahci_port_base(mmio, i);
port_mmio = (u8 *) probe_ent->port[i].port_mmio;
- ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
+ ahci_setup_port(&probe_ent->port[i], mmio, i);
/* make sure port is not active */
tmp = readl(port_mmio + PORT_CMD);
writel(1 << i, mmio + HOST_IRQ_STAT);
- /* set irq mask (enables interrupts) */
- writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
-
/* register linkup ports */
tmp = readl(port_mmio + PORT_SCR_STAT);
debug("SATA port %d status: 0x%x\n", i, tmp);
pci_dev_t pdev = probe_ent->dev;
u16 cc;
#endif
- volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
+ void __iomem *mmio = probe_ent->mmio_base;
u32 vers, cap, cap2, impl, speed;
const char *speed_s;
const char *scc_s;
probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
- pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
- debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
+ probe_ent->mmio_base = pci_map_bar(pdev, PCI_BASE_ADDRESS_5,
+ PCI_REGION_MEM);
+ debug("ahci mmio_base=0x%p\n", probe_ent->mmio_base);
/* Take from kernel:
* JMicron-specific fixup:
for (i = 0; i < sg_count; i++) {
ahci_sg->addr =
- cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
+ cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
ahci_sg->addr_hi = 0;
ahci_sg->flags_size = cpu_to_le32(0x3fffff &
(buf_len < MAX_DATA_BYTE_COUNT
{
pp->cmd_slot->opts = cpu_to_le32(opts);
pp->cmd_slot->status = 0;
- pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
- pp->cmd_slot->tbl_addr_hi = 0;
+ pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
+#ifdef CONFIG_PHYS_64BIT
+ pp->cmd_slot->tbl_addr_hi =
+ cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
+#endif
}
static void ahci_set_feature(u8 port)
{
struct ahci_ioports *pp = &(probe_ent->port[port]);
- volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ void __iomem *port_mmio = pp->port_mmio;
u32 cmd_fis_len = 5; /* five dwords */
u8 fis[20];
}
#endif
+static int wait_spinup(void __iomem *port_mmio)
+{
+ ulong start;
+ u32 tf_data;
+
+ start = get_timer(0);
+ do {
+ tf_data = readl(port_mmio + PORT_TFDATA);
+ if (!(tf_data & ATA_BUSY))
+ return 0;
+ } while (get_timer(start) < WAIT_MS_SPINUP);
+
+ return -ETIMEDOUT;
+}
static int ahci_port_start(u8 port)
{
struct ahci_ioports *pp = &(probe_ent->port[port]);
- volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ void __iomem *port_mmio = pp->port_mmio;
u32 port_status;
- u32 mem;
+ void __iomem *mem;
debug("Enter start port: %d\n", port);
port_status = readl(port_mmio + PORT_SCR_STAT);
return -1;
}
- mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
+ mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
if (!mem) {
free(pp);
printf("%s: No mem for table!\n", __func__);
return -ENOMEM;
}
- mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
- memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
+ /* Aligned to 2048-bytes */
+ mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
+ memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
/*
* First item in chunk of DMA memory: 32-slot command table,
*/
pp->cmd_slot =
(struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
- debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
+ debug("cmd_slot = %p\n", pp->cmd_slot);
mem += (AHCI_CMD_SLOT_SZ + 224);
/*
* and its scatter-gather table
*/
pp->cmd_tbl = virt_to_phys((void *)mem);
- debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
+ debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
mem += AHCI_CMD_TBL_HDR;
pp->cmd_tbl_sg =
(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
- writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
+ writel_with_flush((unsigned long)pp->cmd_slot,
+ port_mmio + PORT_LST_ADDR);
writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
debug("Exit start port %d\n", port);
- return 0;
+ /*
+ * Make sure interface is not busy based on error and status
+ * information from task file data register before proceeding
+ */
+ return wait_spinup(port_mmio);
}
{
struct ahci_ioports *pp = &(probe_ent->port[port]);
- volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ void __iomem *port_mmio = pp->port_mmio;
u32 opts;
u32 port_status;
int sg_count;
ahci_fill_cmd_slot(pp, opts);
ahci_dcache_flush_sata_cmd(pp);
- ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
+ ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
return -1;
}
- ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
+ ahci_dcache_invalidate_range((unsigned long)buf,
+ (unsigned long)buf_len);
debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
return 0;
*/
static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
{
- u32 lba = 0;
+ lbaint_t lba = 0;
u16 blocks = 0;
u8 fis[20];
u8 *user_buffer = pccb->pdata;
u32 user_buffer_size = pccb->datalen;
/* Retrieve the base LBA number from the ccb structure. */
- memcpy(&lba, pccb->cmd + 2, sizeof(lba));
- lba = be32_to_cpu(lba);
+ if (pccb->cmd[0] == SCSI_READ16) {
+ memcpy(&lba, pccb->cmd + 2, 8);
+ lba = be64_to_cpu(lba);
+ } else {
+ u32 temp;
+ memcpy(&temp, pccb->cmd + 2, 4);
+ lba = be32_to_cpu(temp);
+ }
/*
- * And the number of blocks.
+ * Retrieve the base LBA number and the block count from
+ * the ccb structure.
*
* For 10-byte and 16-byte SCSI R/W commands, transfer
* length 0 means transfer 0 block of data.
*
* WARNING: one or two older ATA drives treat 0 as 0...
*/
- blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
+ if (pccb->cmd[0] == SCSI_READ16)
+ blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
+ else
+ blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
- debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
- is_write ? "write" : "read", (unsigned)lba, blocks);
+ debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
+ is_write ? "write" : "read", blocks, lba);
/* Preset the FIS */
memset(fis, 0, sizeof(fis));
u16 now_blocks; /* number of blocks per iteration */
u32 transfer_size; /* number of bytes per iteration */
- now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
+ now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
transfer_size = ATA_SECT_SIZE * now_blocks;
if (transfer_size > user_buffer_size) {
return -EIO;
}
- /* LBA48 SATA command but only use 32bit address range within
- * that. The next smaller command range (28bit) is too small.
+ /*
+ * LBA48 SATA command but only use 32bit address range within
+ * that (unless we've enabled 64bit LBA support). The next
+ * smaller command range (28bit) is too small.
*/
fis[4] = (lba >> 0) & 0xff;
fis[5] = (lba >> 8) & 0xff;
fis[6] = (lba >> 16) & 0xff;
fis[7] = 1 << 6; /* device reg: set LBA mode */
fis[8] = ((lba >> 24) & 0xff);
+#ifdef CONFIG_SYS_64BIT_LBA
+ if (pccb->cmd[0] == SCSI_READ16) {
+ fis[9] = ((lba >> 32) & 0xff);
+ fis[10] = ((lba >> 40) & 0xff);
+ }
+#endif
+
fis[3] = 0xe0; /* features */
/* Block (sector) count */
/* Read/Write from ahci */
if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
- user_buffer, user_buffer_size,
+ user_buffer, transfer_size,
is_write)) {
debug("scsi_ahci: SCSI %s10 command failure.\n",
is_write ? "WRITE" : "READ");
int ret;
switch (pccb->cmd[0]) {
+ case SCSI_READ16:
case SCSI_READ10:
ret = ata_scsiop_read_write(pccb, 0);
break;
}
#ifdef CONFIG_SCSI_AHCI_PLAT
-int ahci_init(u32 base)
+int ahci_init(void __iomem *base)
{
int i, rc = 0;
u32 linkmap;
{
u8 fis[20];
struct ahci_ioports *pp = &(probe_ent->port[port]);
- volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
+ void __iomem *port_mmio = pp->port_mmio;
u32 cmd_fis_len = 5; /* five dwords */
/* Preset the FIS */
}
-void scsi_bus_reset(void)
+__weak void scsi_bus_reset(void)
{
/*Not implement*/
}
-
void scsi_print_error(ccb * pccb)
{
/*The ahci error info can be read in the ahci driver*/
projects / oweals / u-boot.git / blobdiff