+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
* Terry Lv <r65388@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
-#include <libata.h>
+#include <common.h>
#include <ahci.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <dwc_ahsata.h>
#include <fis.h>
-#include <sata.h>
-
-#include <common.h>
+#include <libata.h>
#include <malloc.h>
-#include <linux/ctype.h>
-#include <linux/errno.h>
+#include <memalign.h>
+#include <sata.h>
#include <asm/io.h>
-#include <linux/bitops.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#include "dwc_ahsata.h"
+#include <asm/mach-imx/sata.h>
+#include <linux/bitops.h>
+#include <linux/ctype.h>
+#include <linux/errno.h>
+#include "dwc_ahsata_priv.h"
struct sata_port_regs {
u32 clb;
#define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
-static int is_ready;
-
static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
{
return base + 0x100 + (port * 0x80);
/* Wait for COMINIT bit 26 (DIAG_X) in SERR */
timeout = 1000;
- while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X)
+ while (!(readl(&port_mmio->serr) & SATA_PORT_SERR_DIAG_X)
&& --timeout)
;
if (timeout <= 0) {
cap & (1 << 13) ? "part " : "");
}
-static int ahci_init_one(int pdev)
-{
- int rc;
- struct ahci_uc_priv *uc_priv = NULL;
-
- uc_priv = malloc(sizeof(struct ahci_uc_priv));
- memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
- uc_priv->dev = pdev;
-
- uc_priv->host_flags = ATA_FLAG_SATA
- | ATA_FLAG_NO_LEGACY
- | ATA_FLAG_MMIO
- | ATA_FLAG_PIO_DMA
- | ATA_FLAG_NO_ATAPI;
-
- uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
-
- /* initialize adapter */
- rc = ahci_host_init(uc_priv);
- if (rc)
- goto err_out;
-
- ahci_print_info(uc_priv);
-
- /* Save the uc_private struct to block device struct */
- sata_dev_desc[pdev].priv = uc_priv;
-
- return 0;
-
-err_out:
- return rc;
-}
-
static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
unsigned char *buf, int buf_len)
{
mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
if (!mem) {
- free(pp);
printf("No mem for table!\n");
return -ENOMEM;
}
static void dwc_ahsata_print_info(struct blk_desc *pdev)
{
printf("SATA Device Info:\n\r");
-#ifdef CONFIG_SYS_64BIT_LBA
- printf("S/N: %s\n\rProduct model number: %s\n\r"
- "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
- pdev->product, pdev->vendor, pdev->revision, pdev->lba);
-#else
printf("S/N: %s\n\rProduct model number: %s\n\r"
- "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
+ "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r",
pdev->product, pdev->vendor, pdev->revision, pdev->lba);
-#endif
}
static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
return blkcnt;
}
-int init_sata(int dev)
+static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
{
- int i;
u32 linkmap;
- struct ahci_uc_priv *uc_priv = NULL;
-
-#if defined(CONFIG_MX6)
- if (!is_mx6dq() && !is_mx6dqp())
- return 1;
-#endif
- if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
- printf("The sata index %d is out of ranges\n\r", dev);
- return -1;
- }
-
- ahci_init_one(dev);
+ int i;
- uc_priv = sata_dev_desc[dev].priv;
linkmap = uc_priv->link_port_map;
if (0 == linkmap) {
printf("No port device detected!\n");
- return 1;
+ return -ENXIO;
}
for (i = 0; i < uc_priv->n_ports; i++) {
return 0;
}
+static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
+ struct blk_desc *pdev)
+{
+ u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
+ u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
+ u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
+ u8 port = uc_priv->hard_port_no;
+ ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
+
+ /* Identify device to get information */
+ dwc_ahsata_identify(uc_priv, id);
+
+ /* Serial number */
+ ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
+ memcpy(pdev->product, serial, sizeof(serial));
+
+ /* Firmware version */
+ ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
+ memcpy(pdev->revision, firmware, sizeof(firmware));
+
+ /* Product model */
+ ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
+ memcpy(pdev->vendor, product, sizeof(product));
+
+ /* Total sectors */
+ pdev->lba = ata_id_n_sectors(id);
+
+ pdev->type = DEV_TYPE_HARDDISK;
+ pdev->blksz = ATA_SECT_SIZE;
+ pdev->lun = 0;
+
+ /* Check if support LBA48 */
+ if (ata_id_has_lba48(id)) {
+ pdev->lba48 = 1;
+ debug("Device support LBA48\n\r");
+ }
+
+ /* Get the NCQ queue depth from device */
+ uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
+ uc_priv->flags |= ata_id_queue_depth(id);
+
+ /* Get the xfer mode from device */
+ dwc_ahsata_xfer_mode(uc_priv, id);
+
+ /* Get the write cache status from device */
+ dwc_ahsata_init_wcache(uc_priv, id);
+
+ /* Set the xfer mode to highest speed */
+ ahci_set_feature(uc_priv, port);
+
+ dwc_ahsata_print_info(pdev);
+
+ return 0;
+}
+
+/*
+ * SATA interface between low level driver and command layer
+ */
+static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
+ struct blk_desc *desc, ulong blknr,
+ lbaint_t blkcnt, void *buffer)
+{
+ u32 rc;
+
+ if (desc->lba48)
+ rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
+ READ_CMD);
+ else
+ rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
+ READ_CMD);
+
+ return rc;
+}
+
+static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
+ struct blk_desc *desc, ulong blknr,
+ lbaint_t blkcnt, const void *buffer)
+{
+ u32 rc;
+ u32 flags = uc_priv->flags;
+
+ if (desc->lba48) {
+ rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
+ WRITE_CMD);
+ if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
+ dwc_ahsata_flush_cache_ext(uc_priv);
+ } else {
+ rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
+ WRITE_CMD);
+ if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
+ dwc_ahsata_flush_cache(uc_priv);
+ }
+
+ return rc;
+}
+
+#if !CONFIG_IS_ENABLED(AHCI)
+static int ahci_init_one(int pdev)
+{
+ int rc;
+ struct ahci_uc_priv *uc_priv = NULL;
+
+ uc_priv = malloc(sizeof(struct ahci_uc_priv));
+ if (!uc_priv)
+ return -ENOMEM;
+
+ memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
+ uc_priv->dev = pdev;
+
+ uc_priv->host_flags = ATA_FLAG_SATA
+ | ATA_FLAG_NO_LEGACY
+ | ATA_FLAG_MMIO
+ | ATA_FLAG_PIO_DMA
+ | ATA_FLAG_NO_ATAPI;
+
+ uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
+
+ /* initialize adapter */
+ rc = ahci_host_init(uc_priv);
+ if (rc)
+ goto err_out;
+
+ ahci_print_info(uc_priv);
+
+ /* Save the uc_private struct to block device struct */
+ sata_dev_desc[pdev].priv = uc_priv;
+
+ return 0;
+
+err_out:
+ if (uc_priv)
+ free(uc_priv);
+ return rc;
+}
+
+int init_sata(int dev)
+{
+ struct ahci_uc_priv *uc_priv = NULL;
+
+#if defined(CONFIG_MX6)
+ if (!is_mx6dq() && !is_mx6dqp())
+ return 1;
+#endif
+ if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
+ printf("The sata index %d is out of ranges\n\r", dev);
+ return -1;
+ }
+
+ ahci_init_one(dev);
+
+ uc_priv = sata_dev_desc[dev].priv;
+
+ return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
+}
+
int reset_sata(int dev)
{
struct ahci_uc_priv *uc_priv;
ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
- u32 rc;
- if (sata_dev_desc[dev].lba48)
- rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt,
- buffer, READ_CMD);
- else
- rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt,
- buffer, READ_CMD);
- return rc;
+ return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
+ buffer);
}
ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
- u32 rc;
struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
- u32 flags = uc_priv->flags;
- if (sata_dev_desc[dev].lba48) {
- rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
- WRITE_CMD);
- if ((flags & SATA_FLAG_WCACHE) &&
- (flags & SATA_FLAG_FLUSH_EXT))
- dwc_ahsata_flush_cache_ext(uc_priv);
- } else {
- rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
- WRITE_CMD);
- if ((flags & SATA_FLAG_WCACHE) &&
- (flags & SATA_FLAG_FLUSH))
- dwc_ahsata_flush_cache(uc_priv);
- }
- return rc;
+ return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
+ buffer);
}
int scan_sata(int dev)
{
- u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
- u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
- u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
- u16 *id;
- u64 n_sectors;
struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
- u8 port = uc_priv->hard_port_no;
struct blk_desc *pdev = &sata_dev_desc[dev];
- id = (u16 *)memalign(ARCH_DMA_MINALIGN,
- roundup(ARCH_DMA_MINALIGN,
- (ATA_ID_WORDS * 2)));
- if (!id) {
- printf("id malloc failed\n\r");
- return -1;
- }
+ return dwc_ahsata_scan_common(uc_priv, pdev);
+}
+#endif /* CONFIG_IS_ENABLED(AHCI) */
- /* Identify device to get information */
- dwc_ahsata_identify(uc_priv, id);
+#if CONFIG_IS_ENABLED(AHCI)
- /* Serial number */
- ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
- memcpy(pdev->product, serial, sizeof(serial));
+int dwc_ahsata_port_status(struct udevice *dev, int port)
+{
+ struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct sata_port_regs *port_mmio;
- /* Firmware version */
- ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
- memcpy(pdev->revision, firmware, sizeof(firmware));
+ port_mmio = uc_priv->port[port].port_mmio;
+ return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
+}
- /* Product model */
- ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
- memcpy(pdev->vendor, product, sizeof(product));
+int dwc_ahsata_bus_reset(struct udevice *dev)
+{
+ struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct sata_host_regs *host_mmio = uc_priv->mmio_base;
- /* Totoal sectors */
- n_sectors = ata_id_n_sectors(id);
- pdev->lba = (u32)n_sectors;
+ setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
+ while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
+ udelay(100);
- pdev->type = DEV_TYPE_HARDDISK;
- pdev->blksz = ATA_SECT_SIZE;
- pdev->lun = 0 ;
+ return 0;
+}
- /* Check if support LBA48 */
- if (ata_id_has_lba48(id)) {
- pdev->lba48 = 1;
- debug("Device support LBA48\n\r");
+int dwc_ahsata_scan(struct udevice *dev)
+{
+ struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct blk_desc *desc;
+ struct udevice *blk;
+ int ret;
+
+ /*
+ * Create only one block device and do detection
+ * to make sure that there won't be a lot of
+ * block devices created
+ */
+ device_find_first_child(dev, &blk);
+ if (!blk) {
+ ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
+ IF_TYPE_SATA, -1, 512, 0, &blk);
+ if (ret) {
+ debug("Can't create device\n");
+ return ret;
+ }
}
- /* Get the NCQ queue depth from device */
- uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
- uc_priv->flags |= ata_id_queue_depth(id);
+ desc = dev_get_uclass_platdata(blk);
+ ret = dwc_ahsata_scan_common(uc_priv, desc);
+ if (ret) {
+ debug("%s: Failed to scan bus\n", __func__);
+ return ret;
+ }
- /* Get the xfer mode from device */
- dwc_ahsata_xfer_mode(uc_priv, id);
+ return 0;
+}
- /* Get the write cache status from device */
- dwc_ahsata_init_wcache(uc_priv, id);
+int dwc_ahsata_probe(struct udevice *dev)
+{
+ struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+ int ret;
- /* Set the xfer mode to highest speed */
- ahci_set_feature(uc_priv, port);
+#if defined(CONFIG_MX6)
+ setup_sata();
+#endif
+ uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
+ ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
+ uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
- free((void *)id);
+ /* initialize adapter */
+ ret = ahci_host_init(uc_priv);
+ if (ret)
+ return ret;
- dwc_ahsata_print_info(&sata_dev_desc[dev]);
+ ahci_print_info(uc_priv);
- is_ready = 1;
+ return dwc_ahci_start_ports(uc_priv);
+}
- return 0;
+static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
+ lbaint_t blkcnt, void *buffer)
+{
+ struct blk_desc *desc = dev_get_uclass_platdata(blk);
+ struct udevice *dev = dev_get_parent(blk);
+ struct ahci_uc_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
}
+
+static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
+ lbaint_t blkcnt, const void *buffer)
+{
+ struct blk_desc *desc = dev_get_uclass_platdata(blk);
+ struct udevice *dev = dev_get_parent(blk);
+ struct ahci_uc_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
+}
+
+static const struct blk_ops dwc_ahsata_blk_ops = {
+ .read = dwc_ahsata_read,
+ .write = dwc_ahsata_write,
+};
+
+U_BOOT_DRIVER(dwc_ahsata_blk) = {
+ .name = "dwc_ahsata_blk",
+ .id = UCLASS_BLK,
+ .ops = &dwc_ahsata_blk_ops,
+};
+
+#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
+struct ahci_ops dwc_ahsata_ahci_ops = {
+ .port_status = dwc_ahsata_port_status,
+ .reset = dwc_ahsata_bus_reset,
+ .scan = dwc_ahsata_scan,
+};
+
+static const struct udevice_id dwc_ahsata_ahci_ids[] = {
+ { .compatible = "fsl,imx6q-ahci" },
+ { }
+};
+
+U_BOOT_DRIVER(dwc_ahsata_ahci) = {
+ .name = "dwc_ahsata_ahci",
+ .id = UCLASS_AHCI,
+ .of_match = dwc_ahsata_ahci_ids,
+ .ops = &dwc_ahsata_ahci_ops,
+ .probe = dwc_ahsata_probe,
+};
+#endif
+#endif
projects / oweals / u-boot.git / blobdiff