Merge branch 'master' of git://git.denx.de/u-boot-samsung

[oweals/u-boot.git] / doc / README.x86

diff --git a/doc/README.x86 b/doc/README.x86
index 3bab5cf64e62902240a705e32aa3290205cd596f..6cf293b11ec3aa90ba0bbe3e5169233c77ea1c5d 100644 (file)
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -189,7 +189,7 @@ Offset   Description         Controlling config
 001000   me.bin              Set by the descriptor
 500000   <spare>
 700000   u-boot-dtb.bin      CONFIG_SYS_TEXT_BASE
-790000   vga.bin             CONFIG_X86_OPTION_ROM_ADDR
+790000   vga.bin             CONFIG_VGA_BIOS_ADDR
 7c0000   fsp.bin             CONFIG_FSP_ADDR
 7f8000   <spare>             (depends on size of fsp.bin)
 7fe000   Environment         CONFIG_ENV_OFFSET
@@ -733,11 +733,36 @@ Example output:
    PCI_BDF(0, 3, 0) INTA PIRQA
 ...
 
+Porting Hints
+-------------
+
+Quark-specific considerations:
+
+To port U-Boot to other boards based on the Intel Quark SoC, a few things need
+to be taken care of. The first important part is the Memory Reference Code (MRC)
+parameters. Quark MRC supports memory-down configuration only. All these MRC
+parameters are supplied via the board device tree. To get started, first copy
+the MRC section of arch/x86/dts/galileo.dts to your board's device tree, then
+change these values by consulting board manuals or your hardware vendor.
+Available MRC parameter values are listed in include/dt-bindings/mrc/quark.h.
+The other tricky part is with PCIe. Quark SoC integrates two PCIe root ports,
+but by default they are held in reset after power on. In U-Boot, PCIe
+initialization is properly handled as per Quark's firmware writer guide.
+In your board support codes, you need provide two routines to aid PCIe
+initialization, which are board_assert_perst() and board_deassert_perst().
+The two routines need implement a board-specific mechanism to assert/deassert
+PCIe PERST# pin. Care must be taken that in those routines that any APIs that
+may trigger PCI enumeration process are strictly forbidden, as any access to
+PCIe root port's configuration registers will cause system hang while it is
+held in reset. For more details, check how they are implemented by the Intel
+Galileo board support codes in board/intel/galileo/galileo.c.
+
 TODO List
 ---------
 - Audio
 - Chrome OS verified boot
 - SMI and ACPI support, to provide platform info and facilities to Linux
+- Desktop Management Interface (DMI) [15] support
 
 References
 ----------
@@ -755,3 +780,4 @@ References
 [12] http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf
 [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
 [14] doc/device-tree-bindings/misc/intel,irq-router.txt
+[15] http://en.wikipedia.org/wiki/Desktop_Management_Interface