Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
will be left empty (M66EN high), and so the board will operate with
-a base clock of 66MHz. Note that you need both PCI enabled in u-boot
+a base clock of 66MHz. Note that you need both PCI enabled in u-boot
and linux in order to have functional PCI under linux.
The second enables PCI support and builds for a 33MHz clock rate. Note
to reflect a different CCB:SYSCLK ratio]
The third option builds PCI support in, and leaves the clocking at the
-default 66MHz. Options four and five are just repeats of option two
+default 66MHz. Options four and five are just repeats of option two
and three, but with PCI-e support enabled as well.
PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
-is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
+is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with
a 33MHz PCI configuration is currently untested.)
=> pci 0
Scanning PCI devices on bus 0
- BusDevFun VendorId DeviceId Device Class Sub-Class
+ BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
- 00.00.00 0x1057 0x0012 Processor 0x20
- 00.01.00 0x8086 0x1026 Network controller 0x00
+ 00.00.00 0x1057 0x0012 Processor 0x20
+ 00.01.00 0x8086 0x1026 Network controller 0x00
=> pci 1
Scanning PCI devices on bus 1
- BusDevFun VendorId DeviceId Device Class Sub-Class
+ BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
- 01.00.00 0x1957 0x0012 Processor 0x20
+ 01.00.00 0x1957 0x0012 Processor 0x20
=> pci 2
Scanning PCI devices on bus 2
- BusDevFun VendorId DeviceId Device Class Sub-Class
+ BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
- 02.00.00 0x1148 0x9e00 Network controller 0x00
+ 02.00.00 0x1148 0x9e00 Network controller 0x00
=>
Memory Size and using SPD:
There is a hardware errata, which causes the older local bus SDRAM
SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
-that the SPD data can not be read reliably.
+that the SPD data can not be read reliably. You can test if your
+board has the errata fix by running "i2c probe". If you see 0x53
+as a valid device, it has been fixed. If you only see 0x50, 0x51
+then your board does not have the fix.
+
+You can also visually inspect the board to see if this hardware
+fix has been applied:
+
+ 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
+ the back of the PCB behind the DDR SDRAM SODIMM connector.
+ 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
+ to R313 pin 2. Pin 2 for each resistor is the end of the
+ resistor closest to the CPU.
+
+Boards without the mod will have R314 and R313 in parallel, like "||".
+After the mod, they will be touching and form an "L" shape.
If you want to upgrade to larger RAM size, you can simply enable
#define CONFIG_SPD_EEPROM
in include/configs/sbc8548.h file. (The lines are already there
but listed as #undef).
-Note that you will have to physically remove the LBC 128MB DIMM
+If you did the i2c test, and your board does not have the errata
+fix, then you will have to physically remove the LBC 128MB DIMM
from the board's socket to resolve the above i2c address overlap
issue and allow SPD autodetection of RAM to work.
===================
The following contains some summary information on hardware settings
-that are relevant to u-boot, based on the board manual. For the
+that are relevant to u-boot, based on the board manual. For the
most up to date and complete details of the board, please request the
reference manual ERG-00327-001.pdf from www.windriver.com
projects / oweals / u-boot.git / blobdiff